PIC16LF874-04/PQ Microchip Technology, PIC16LF874-04/PQ Datasheet - Page 174
![IC PIC MCU FLASH 4KX14 44MQFP](/photos/6/59/65984/150-44-pqfp_sml.jpg)
PIC16LF874-04/PQ
Manufacturer Part Number
PIC16LF874-04/PQ
Description
IC PIC MCU FLASH 4KX14 44MQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F873-04SO.pdf
(218 pages)
Specifications of PIC16LF874-04/PQ
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-MQFP, 44-PQFP
Core
PIC
Processor Series
PIC16LF
Data Bus Width
8 bit
Maximum Clock Frequency
20 MHz
Data Ram Size
192 B
Data Rom Size
128 B
On-chip Adc
8
Number Of Programmable I/os
33
Number Of Timers
3 bit
Operating Supply Voltage
2 V to 5.5 V
Mounting Style
SMD/SMT
Height
2 mm
Interface Type
MSSP, PSP, USART
Length
10 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2 V
Width
10 mm
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16LF874-04/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC16F87X
TABLE 15-9:
DS30292C-page 172
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
Param
No.
100
101
102
103
106
107
109
110
90
91
92
2: A fast mode (400 kHz) I
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
Tsu:dat
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
T
released.
R
max.+ Tsu:dat = 1000 + 250 = 1250 ns (according to the standard mode I
Thd:sta
Thd:dat
Tsu:sta
Tsu:dat
Tsu:sto
Thigh
Sym
Tlow
Tbuf
Taa
Cb
Tr
Tf
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
I
2
C BUS DATA REQUIREMENTS
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall time 100 kHz mode
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
2
C bus device can be used in a standard mode (100 kHz) I
Characteristic
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1Cb
20 + 0.1Cb
0.5T
0.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
1000
3500
Max
300
300
300
0.9
400
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C bus specification) before the SCL line is
2
C bus system, but the requirement that
Units
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
s
2001 Microchip Technology Inc.
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for Repeated
START condition
After this period, the first clock
pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
Conditions
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