PIC24FJ256GB110-I/PF Microchip Technology, PIC24FJ256GB110-I/PF Datasheet - Page 178

• Manufacturer Part Number: PIC24FJ256GB110-I/PF
• Description: IC PIC MCU FLASH 256K 100TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB110-I/PF

• Program Memory Type: FLASH
• Program Memory Size: 256KB (85.5K x 24)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 83
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 84
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FJ256GB110 FAMILY
FIGURE 14-3:
FIGURE 14-4:
DS39897B-page 176
Note
PROCESSOR 1 (SPI Enhanced Buffer Master)
Note
1:
2:
1:
2:
PROCESSOR 1 (SPI Master)
MSTEN (SPIxCON1<5>) = 1 and
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
SPIBEN (SPIxCON2<0>) = 1
MSTEN (SPIxCON1<5>) = 1)
Using the SSx pin in Slave mode of operation is optional.
User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory
mapped to SPIxBUF.
MSb
MSb
SPI MASTER/SLAVE CONNECTION (STANDARD MODE)
SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
8-Level FIFO Buffer
Serial Transmit Buffer
Serial Receive Buffer
Shift Register
SPIx Buffer
(SPIxBUF)
(SPIxSR)
Shift Register
SPIx Buffer
(SPIxRXB)
(SPIxBUF)
(SPIxTXB)
(SPIxSR)
LSb
LSb
SDOx
SCKx
SDIx
SDOx
SDIx
SCKx
SSx
Preliminary
Serial Clock
Serial Clock
SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0
SDIx
SDOx
SCKx
SSx
SCKx
SDIx
SDOx
SSx
PROCESSOR 2 (SPI Enhanced Buffer Slave)
PROCESSOR 2 (SPI Slave)
MSb
Serial Transmit Buffer
Serial Receive Buffer
MSTEN (SPIxCON1<5>) = 0 and
SSEN (SPIxCON1<7>) = 1,
SPIBEN (SPIxCON2<0>) = 1
Shift Register
SPIx Buffer
(SPIxRXB)
MSb
(SPIxTXB)
(SPIxBUF)
(SPIxSR)
8-Level FIFO Buffer
Shift Register
SPIx Buffer
(SPIxBUF)
(SPIxSR)
© 2008 Microchip Technology Inc.
LSb
LSb