PIC24HJ256GP210-I/PF Microchip Technology, PIC24HJ256GP210-I/PF Datasheet - Page 53
![IC PIC MCU FLASH 128KX16 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ256GP210-I/PF
Manufacturer Part Number
PIC24HJ256GP210-I/PF
Description
IC PIC MCU FLASH 128KX16 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP206-IPT.pdf
(286 pages)
Specifications of PIC24HJ256GP210-I/PF
Program Memory Type
FLASH
Program Memory Size
256KB (85.5K x 24)
Package / Case
100-TQFP, 100-VQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b, 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
CAN/I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
85
Ram Memory Size
16KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
A/d Bit Size
12 bit
A/d Channels Available
32
Height
1 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
14 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164323 - MODULE SKT FOR 100TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ256GP210-I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24HJ256GP210-I/PF
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
3.4.2
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH instruc-
tions are the only method to read or write the upper
8 bits of a program space word as data.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit,
word wide address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space which contains the least significant
data word and TBLRDH and TBLWTH access the space
which contains the upper data byte.
Two table instructions are provided to move byte or
word sized (16-bit) data to and from program space.
Both function as either byte or word operations.
1.
FIGURE 3-7:
© 2007 Microchip Technology Inc.
TBLRDL (Table Read Low): In Word mode, it
maps the lower word of the program space
location (P<15:0>) to a data address (D<15:0>).
In Byte mode, either the upper or lower byte of
the lower program word is mapped to the lower
byte of a data address. The upper byte is
selected when Byte Select is ‘1’; the lower byte
is selected when it is ‘0’.
TBLPAG
02
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
23
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
15
0
0x000000
0x020000
0x030000
0x800000
PIC24HJXXXGPX06/X08/X10
Program Space
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
2.
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 4.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user and config-
uration spaces. When TBLPAG<7> = 0, the table page
is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
‘Phantom’ Byte
00000000
00000000
00000000
00000000
TBLRDH (Table Read High): In Word mode, it
maps the entire upper word of a program address
(P<23:16>) to a data address. Note that
D<15:8>, the ‘phantom byte’, will always be ‘0’.
In Byte mode, it maps the upper or lower byte of
the program word to D<7:0> of the data
address, as above. Note that the data will
always be ‘0’ when the upper ‘phantom’ byte is
selected (Byte Select = 1).
23
16
8
DS70175F-page 51
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