PIC18F4220-I/ML Microchip Technology, PIC18F4220-I/ML Datasheet - Page 40
![IC MCU FLASH 2KX16 EEPROM 44QFN](/photos/6/81/68122/150-44-qfn_sml.jpg)
PIC18F4220-I/ML
Manufacturer Part Number
PIC18F4220-I/ML
Description
IC MCU FLASH 2KX16 EEPROM 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-I/ML
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F1320-ISS PDF datasheet #2
- PIC18F2220-ISO PDF datasheet #3
- PIC18F2220-ISO PDF datasheet #4
- PIC18F2220-ISO PDF datasheet #5
- PIC18F2220-ISO PDF datasheet #6
- PIC18F2220-ISO PDF datasheet #7
- PIC18F2220-ISO PDF datasheet #8
- Current page: 40 of 394
- Download datasheet (7Mb)
PIC18F2220/2320/4220/4320
3.4.4
An exit from a power-managed Run mode to its corre-
sponding Idle mode is executed by setting the IDLEN
bit and executing a SLEEP instruction. The CPU is
halted at the beginning of the instruction following the
SLEEP instruction. There are no changes to any of the
clock source status bits (OSTS, IOFS or T1RUN).
While the CPU is halted, the peripherals continue to be
clocked from the previously selected clock source.
3.4.5
An exit from a power-managed Run mode to Sleep
mode is executed by clearing the IDLEN and
SCS1:SCS0 bits and executing a SLEEP instruction.
The code is no different than the method used to invoke
Sleep mode from the normal operating (full power)
mode.
The primary clock and internal oscillator block are dis-
abled. The INTRC will continue to operate if the WDT
is enabled. The Timer1 oscillator will continue to run, if
enabled, in the T1CON register. All clock source status
bits are cleared (OSTS, IOFS and T1RUN).
DS39599G-page 38
EXIT TO IDLE MODE
EXIT TO SLEEP MODE
3.5
An exit from any of the power-managed modes is trig-
gered by an interrupt, a Reset, or a WDT time-out. This
section discusses the triggers that cause exits from
power-managed modes. The clocking subsystem
actions are discussed in each of the power-managed
modes (see Section 3.2 “Sleep Mode” through
Section 3.4 “Run Modes”).
Device behavior during Low-Power mode exits is
summarized in Table 3-3.
3.5.1
Any of the available interrupt sources can cause the
device to exit a power-managed mode and resume full-
power operation. To enable this functionality, an
interrupt source must be enabled by setting its enable
bit in one of the INTCON or PIE registers. The exit
sequence is initiated when the corresponding interrupt
flag bit is set. On all exits from Lower Power mode by
interrupt, code execution branches to the interrupt
vector if the GIE/GIEH bit (INTCON<7>) is set. Other-
wise, code execution continues or resumes without
branching (see Section 9.0 “Interrupts”).
Note:
Wake-up From Power-Managed
Modes
If application code is timing sensitive, it
should wait for the OSTS bit to become set
before continuing. Use the interval during
the low-power exit sequence (before
OSTS is set) to perform timing insensitive
“housekeeping” tasks.
EXIT BY INTERRUPT
© 2007 Microchip Technology Inc.
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