ATMEGA32-16MU Atmel, ATMEGA32-16MU Datasheet - Page 19
![IC AVR MCU 32K 16MHZ 5V 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA32-16MU
Manufacturer Part Number
ATMEGA32-16MU
Description
IC AVR MCU 32K 16MHZ 5V 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32-16MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Changes from Rev.
2503D-02/03 to
Rev. 2503E-09/03
Changes from Rev.
2503C-10/02 to
Rev. 2503D-02/03
Changes from Rev.
2503B-10/02 to
Rev. 2503C-10/02
Changes from Rev.
2503A-03/02 to
Rev. 2503B-10/02
2503QS–AVR–02/11
1. Updated and changed “On-chip Debug System” to
2. Updated
3. Updated
4. Updated description for Bit 7 – JTD: JTAG Interface Disable on
5. Added a note regarding JTAGEN fuse to
6. Updated Absolute Maximum Ratings* , DC Characteristics and ADC Characteristics in
7. Added a proposal for solving problems regarding the JTAG instruction IDCODE in
1. Added EEAR9 in EEARH in
2. Added Chip Erase as a first step
3. Removed reference to “Multi-purpose Oscillator” application note and “32 kHz Crys-
4. Added information about PWM symmetry for Timer0 and Timer2.
5. Added note in
6. Added “Power Consumption” data in
7. Added section
8. Added note about Differential Mode with Auto Triggering in
9. Updated
10.Added updated
1. Updated the
1. Canged the endurance on the Flash to 10,000 Write/Erase Cycles.
2. Bit nr.4 – ADHSM – in SFIOR Register removed.
3. Added the section
4. When using External Clock there are some limitations regards to change of fre-
Debug System” on page
“Electrical Characteristics” on page
“Errata” on page
gramming the EEPROM” on page
tal Oscillator” application note, which do not exist.
ing to the EEPROM during an SPM Page Load.
sion Timing” on page
quency. This is described in
Table 15 on page
“Test Access Port – TAP” on page 219
Table 89 on page
“DC Characteristics” on page
“Filling the Temporary Buffer (Page Loading)” on page 251
“Packaging Information” on page
“EEPROM Write During Power-down Sleep Mode” on page
336.
“Default Clock Source” on page
204.
35.
37.
232.
“Register Summary” on page
“External Clock” on page 31
in“Programming the Flash” on page 284
285.
287.
“Features” on page
Table 104 on page
287.
regarding the JTAGEN fuse.
333.
25.
“JTAG Interface and On-chip
327.
and
1.
257.
“Prescaling and Conver-
ATmega32(L)
Table 117 on page
page
228.
22.
about writ-
and
“Pro-
289.
19