PIC16C63-04I/SO Microchip Technology, PIC16C63-04I/SO Datasheet - Page 97
![IC MCU OTP 4KX14 PWM 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16C63-04I/SO
Manufacturer Part Number
PIC16C63-04I/SO
Description
IC MCU OTP 4KX14 PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16LC62A-04SP.pdf
(337 pages)
3.PIC16C63-04SP.pdf
(8 pages)
Specifications of PIC16C63-04I/SO
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
- Current page: 97 of 337
- Download datasheet (3Mb)
Figure 11-19 and Figure 11-20 show Master-transmit-
ter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
FIGURE 11-21: COMBINED FORMAT
Transfer direction of data and acknowledgment bits depends on R/W bits.
Sr
A master reads a slave immediately after the first byte.
Combined format - A master addresses a slave with a 10-bit address, then transmits
1997 Microchip Technology Inc.
For 7-bit address:
Combined format:
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
S
S
For 7-bit address:
Slave Address
S
From slave to master
From master to slave
Slave Address R/W A Data A Data A P
Slave Address R/W A Data A/A Sr
From slave to master
From master to slave
First 7 bits
Slave Address R/W A Data A Data A/A P
From slave to master
From master to slave
'1' (read)
'0' (write)
(write)
(read)
R/W A
data to this slave and reads data from this slave.
(n bytes - acknowledge)
(n bytes - acknowledge)
Slave Address
Second byte
data transferred
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
data transferred
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Sr = repeated
Start Condition
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
(n bytes + acknowledge)
(read or write)
Slave Address R/W A Data A/A
A
Data
A
(write)
Data A/A
For 10-bit address:
S
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
For 10-bit address:
S
Slave Address
Direction of transfer
may change at this point
Slave Address
First 7 bits
A master transmitter addresses a slave receiver
with a 10-bit address.
First 7 bits
Sr Slave Address
A master transmitter addresses a slave receiver
with a 10-bit address.
Sr
Slave Address
(write)
Data A
First 7 bits
(write)
First 7 bits
P
R/W A1 Slave Address
R/W A1 Slave Address
(read)
(read)
Data
R/W A Data A
R/W A3
Second byte
Second byte
A/A
PIC16C6X
P
Data A
DS30234D-page 97
A2
A2
Data
Data
A
A P
P
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