PIC18F4220-I/PT Microchip Technology, PIC18F4220-I/PT Datasheet - Page 14
![IC MCU FLASH 2KX16 A/D 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4220-I/PT
Manufacturer Part Number
PIC18F4220-I/PT
Description
IC MCU FLASH 2KX16 A/D 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F1320-ISS.pdf
(36 pages)
3.PIC18F2220-ISO.pdf
(394 pages)
4.PIC18F2220-ISO.pdf
(6 pages)
5.PIC18F2220-ISO.pdf
(6 pages)
6.PIC18F2220-ISO.pdf
(8 pages)
7.PIC18F2220-ISO.pdf
(6 pages)
8.PIC18F2220-ISO.pdf
(6 pages)
Specifications of PIC18F4220-I/PT
Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Core
PIC
Processor Series
PIC18F
Data Bus Width
8 bit
Maximum Clock Frequency
40 MHz
Data Ram Size
512 B
Data Rom Size
256 B
On-chip Adc
Yes
Number Of Programmable I/os
36
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
13
Height
1 mm
Interface Type
SPI, I2C, USART
Length
10 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4220-I/PT
Manufacturer:
SST
Quantity:
1 150
Company:
Part Number:
PIC18F4220-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18FX220/X320
FIGURE 3-6:
3.3.1
All of the programming examples, up to this point, have
assumed that the device is blank prior to programming.
In fact, if the device is not blank, the direction has been
to completely erase the device via a Bulk Erase
operation (see Section 3.2 “High-Voltage ICSP Bulk
Erase”).
It may be the case, however, that the user wishes to
modify only a section of an already programmed
device. In such a situation, erasing the entire device is
not a realistic option.
The minimum amount of data that can be written to the
device is 8 bytes. This is accomplished by loading the
8-byte write buffer for the panel and then initiating a
write sequence. In this case, however, it is assumed
that the address space to be written already has data in
it (i.e., it is not blank).
The minimum amount of code memory that may be
erased at a given time is one row of 64 bytes and it is
selected using the TBLPTR registers. The sixth LSb of
the TBLPTR address is ignored. The EECON1 register
must then be used to erase the 64-byte target space
prior to writing the data. This is known as a “Row
Erase”.
DS39592F-page 14
PGC
PGD
1
1
4-Bit Command
MODIFYING CODE MEMORY
2
1
3
1
4
1
TABLE WRITE AND START PROGRAMMING INSTRUCTION TIMING (1111)
P5
1
n
2
n
3
16-Bit Data Payload
n
4
n
5
n
6
n
15 16
PGD = Input
n
n
P5A
When using the EECON1 register to act on code mem-
ory, the EEPGD bit must be set (EECON1<7> = 1) and
the CFGS bit must be cleared (EECON1<6> = 0). The
WREN bit must be set (EECON1<2> = 1) to enable
writes of any sort (e.g., erases), and this must be done
prior to initiating a write sequence. The FREE bit must
be set (EECON1<4> = 1) in order to erase the program
space being pointed to by the Table Pointer. The erase
sequence is initiated by the setting the WR bit
(EECON1<1> = 1). It is strongly recommended that the
WREN bit be set only when absolutely necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h,
and then 0AAh, immediately prior to asserting the WR
bit in order for the write to occur.
The erase will begin on the falling edge of the 4th PGC
after the WR bit is set.
After the erase sequence terminates, PGC must still be
held low for the time specified by parameter P10 to
allow high-voltage discharge of the memory array.
4-Bit Command
1
0
2
0
3
0
0
Programming Time
P9
2010 Microchip Technology Inc.
4
P10
Data Payload
1
0
16-Bit
2
0
3
0