ATMEGA644P-20AU Atmel, ATMEGA644P-20AU Datasheet - Page 84
![IC MCU AVR 64K FLASH 44-TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA644P-20AU
Manufacturer Part Number
ATMEGA644P-20AU
Description
IC MCU AVR 64K FLASH 44-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA164P-20AU.pdf
(28 pages)
2.ATMEGA164P-20AU.pdf
(439 pages)
3.ATMEGA324P-20AU.pdf
(26 pages)
Specifications of ATMEGA644P-20AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
ATMEGA64x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
2-Wire, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 channel
A/d Inputs
8-Channel, 10-Bit
Cpu Speed
20 MIPS
Eeprom Memory
2K Bytes
Input Output
32
Interface
2-Wire/JTAG/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin TQFP
Programmable Memory
64K Bytes
Timers
2-8-bit, 1-16-bit
Voltage, Range
2.7-5.5 V
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
4KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Controller Family/series
AVR MEGA
No. Of I/o's
32
Eeprom Memory Size
2KB
Ram Memory Size
4KB
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA644P-20AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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8011O–AVR–07/10
• T0/XCK0/PCINT8, Bit 0
T0, Timer/Counter0 counter source.
XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock
is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the
USART0 operates in Synchronous mode.
PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.
Table 11-7
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. .
Table 11-7.
Table 11-8.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 11-5 on page
PB7/SCK/
PCINT15
SPE • MSTR
PORTB7 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT15 • PCIE1
1
SCK INPUT
PCINT17 INPUT
–
PB3/AIN1/OC0B/
PCINT11
0
0
0
0
OC0B ENABLE
OC0B
PCINT11 • PCIE1
1
PCINT11 INPUT
AIN1 INPUT
and
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
Table 11-8
relate the alternate functions of Port B to the overriding signals
78. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/MISO/
PCINT14
SPE • MSTR
PORTB14 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
PCINT14 • PCIE1
1
SPI MSTR INPUT
PCINT14 INPUT
–
PB2/AIN0/INT2/
PCINT10
0
0
0
0
0
0
INT2 ENABLE
PCINT10 • PCIE1
1
INT2 INPUT
PCINT10 INPUT
AIN0 INPUT
ATmega164P/324P/644P
PB5/MOSI/
PCINT13
SPE • MSTR
PORTB13 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
PCINT13 • PCIE1
1
SPI SLAVE INPUT
PCINT13 INPUT
–
PB1/T1/CLKO/PCIN
T9
0
0
CKOUT
CKOUT
CKOUT
CLK I/O
PCINT9 • PCIE1
1
T1 INPUT
PCINT9 INPUT
–
PCINT12 • PCIE1
PB4/SS/OC0B/
PCINT12
SPE • MSTR
PORTB12 • PUD
SPE • MSTR
0
OC0A ENABLE
OC0A
1
SPI SS
PCINT12 INPUT
–
PB0/T0/XCK/
PCINT8
0
0
0
0
0
0
PCINT8 • PCIE1
1
T0 INPUT
PCINT8 INPUT
–
84
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