PIC16C63-20/SO Microchip Technology, PIC16C63-20/SO Datasheet - Page 101
![IC MCU OTP 4KX14 PWM 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC16C63-20/SO
Manufacturer Part Number
PIC16C63-20/SO
Description
IC MCU OTP 4KX14 PWM 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16LC62A-04SP.pdf
(337 pages)
3.PIC16C63-04SP.pdf
(8 pages)
Specifications of PIC16C63-20/SO
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1073 - ADAPTER 28-SOIC TO 28-SOIC309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
- Current page: 101 of 337
- Download datasheet (3Mb)
11.5.1.2
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT reg-
ister is cleared. The received address is loaded into the
SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
FIGURE 11-25: I
SDA
SCL
SSPIF (PIR1<3>)
1997 Microchip Technology Inc.
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
S
RECEPTION
A7 A6 A5 A4 A3 A2 A1
1
2
Receiving Address
2
3
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
4
5
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
6
7
R/W=0
8
ACK
9
D7
1
D6
2
SSPBUF register is read
Receiving Data
D5
3
Cleared in software
D4
Bit SSPOV is set because the SSPBUF register is still full.
4
D3
5
D2
6
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
D1
7
D0
8
ACK
9
D7
1
D6
2
D5
Receiving Data
3
D4
4
ACK is not sent.
D3
5
PIC16C6X
D2
6
D1
7
DS30234D-page 101
D0
8
ACK
9
Bus Master
terminates
transfer
P
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