ATMEGA329P-20MU Atmel, ATMEGA329P-20MU Datasheet - Page 15

• Manufacturer Part Number: ATMEGA329P-20MU
• Description: IC MCU 32K 4X25 LCD CTRL 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATMEGA329P-16MU; ATMEGA329P-16MU

6.6.1
6.7
8021G–AVR–03/11
Instruction Execution Timing
SPH and SPL – Stack pointer High and Stack Pointer Low
This section describes the general access timing concepts for instruction execution. The
Atmel
source for the chip. No internal clock division is used.
Figure 6-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
Figure 6-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
2nd Instruction Execute
®
3rd Instruction Execute
1st Instruction Execute
AVR
2nd Instruction Fetch
3rd Instruction Fetch
4th Instruction Fetch
1st Instruction Fetch
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
®
CPU is driven by the CPU clock clk
The Parallel Instruction Fetches and Instruction Executions
SP15
R/W
R/W
SP7
15
7
0
0
clk
CPU
SP14
R/W
R/W
SP6
14
6
0
0
SP13
R/W
R/W
SP5
13
5
0
0
T1
SP12
R/W
R/W
SP4
12
4
0
0
CPU
, directly generated from the selected clock
T2
SP11
R/W
R/W
SP3
11
3
0
0
ATmega329P/3290P
SP10
SP2
R/W
R/W
10
2
0
0
T3
SP9
SP1
R/W
R/W
9
1
0
0
SP8
SP0
R/W
R/W
8
0
0
0
T4
SPH
SPL
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