PIC18LF2480-I/ML Microchip Technology, PIC18LF2480-I/ML Datasheet - Page 136
![IC PIC MCU FLASH 8KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18LF2480-I/ML
Manufacturer Part Number
PIC18LF2480-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18LF2480-ISP.pdf
(14 pages)
Specifications of PIC18LF2480-I/ML
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163011, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18LF2480-ISP PDF datasheet #4
- Current page: 136 of 490
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
TABLE 11-1:
DS39637D-page 136
RA0/AN0/CV
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI
RA5/AN4/SS/HLVDIN
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Legend:
Note 1:
Pin Name
REF
REF
OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input
Available on 40/44-pin devices only.
REF
-
+
PORTA I/O SUMMARY
Function
CV
HLVDIN
V
T0CKI
OSC2
CLKO
OSC1
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
RA7
REF
SS
REF
REF
+
(1)
-
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
TRIS
0
1
1
x
0
1
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
x
x
0
1
x
x
0
1
Buffer
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
TTL
DIG
DIG
TTL
DIG
TTL
ST
LATA<0> data output.
PORTA<0> data input.
A/D Input Channel 0. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
Comparator voltage reference analog output. Enabling this analog
output overrides the digital I/O (read as clear – low level).
LATA<1> data output.
PORTA<1> data input.
A/D Input Channel 1. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
LATA<2> data output.
PORTA<2> data input.
A/D Input Channel 2. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
A/D and comparator negative voltage analog input.
LATA<3> data output.
PORTA<3> data input.
A/D Input Channel 3. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
A/D and comparator positive voltage analog input.
LATA<4> data output.
PORTA<4> data input.
Timer0 clock input.
LATA<5> data output.
PORTA<5> data input.
A/D Input Channel 4. Enabled on POR; this analog input overrides the
digital input (read as clear – low level).
Slave select input for MSSP.
High/Low-Voltage Detect external trip point input.
Output connection; selected by FOSC<3:0> Configuration bits.
Enabling OSC2 overrides digital I/O.
Output connection; selected by FOSC<3:0> Configuration bits.
Enabling CLKO overrides digital I/O (F
LATA<6> data output.
PORTA<6> data input.
Main oscillator input connection determined by FOSC<3:0>
Configuration bits. Enabling OSC1 overrides digital I/O.
Main clock input connection determined by FOSC<3:0>
Configuration bits. Enabling CLKI overrides digital I/O.
LATA<7> data output.
PORTA<7> data input.
Description
© 2009 Microchip Technology Inc.
OSC
/4).
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