PIC18F2610-I/SP Microchip Technology, PIC18F2610-I/SP Datasheet - Page 9

• Manufacturer Part Number: PIC18F2610-I/SP
• Description: IC MCU FLASH 32KX16 28-DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2610-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3968 B
• Interface Type: CCP/ECCP/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10-ch x 10-bit
• Package: 28SPDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24. Module: EUSART
25. Module: EUSART
26. Module: EUSART
27. Module: EUSART
© 2007 Microchip Technology Inc.
The EUSART auto-baud feature may occasionally
measure the incoming baud rate incorrectly. The
rate of incorrect baud rate measurements will
depend on the frequency of the incoming
synchronization byte and the system clock
frequency.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In Synchronous mode (SYNC = 1) with clock
polarity high (SCKP = 1), the EUSART transmits a
shorter than expected clock on the CK pin for bit 0.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In Synchronous mode, EUSART baud rates using
SPBRG values of ‘0’ and ‘1’ may not function
correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Date Codes that pertain to this issue:
All engineering and production devices.
During an auto-baud operation, the TX pin is
tri-stated. Transceivers which do not provide a
pull-up on the TX signal may cause the bus to
become
additional bus activity.
Work around
Use pull-up resistor on TX pin.
Date Codes that pertain to this issue:
All engineering and production devices.
inadvertently
active
and
PIC18F2515/2610/4515/4610
prevent
28. Module: MSSP
29. Module: MSSP
30. Module: MSSP
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and the SSPOV bits. In
both situations, the SSPIF bit is not set and an
interrupt will not occur.
Work around
The I
I
Date Codes that pertain to this issue:
All engineering and production devices.
In I
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPADD ≥ ‘1’.
Date Codes that pertain to this issue:
All engineering and production devices.
In I
ware to begin data reception and cleared by the
peripheral after a byte is received. After a byte is
received, the device may delay clearing RCEN.
Work around
Single byte receptions are typically not affected,
since the delay between byte receptions typically
is long enough for the RCEN bit to clear. For mul-
tiple byte receptions, the software must wait until
the bit is cleared before the next byte can be
received.
Date Codes that pertain to this issue:
All engineering and production devices.
2
C event to maintain normal operation.
2
2
C Master mode, the BRG value of ‘0’ may not
C Master mode, the RCEN bit is set by soft-
2
C slave must clear the SSPOV bit after each
2
C system with multiple slave nodes, an
DS80199E-page 9