PIC24HJ128GP210A-I/PT Microchip Technology, PIC24HJ128GP210A-I/PT Datasheet - Page 67
![IC PIC MCU FLASH 128KB 100-TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC24HJ128GP210A-I/PT
Manufacturer Part Number
PIC24HJ128GP210A-I/PT
Description
IC PIC MCU FLASH 128KB 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206A-IMR.pdf
(304 pages)
3.PIC24HJ64GP206A-IMR.pdf
(10 pages)
Specifications of PIC24HJ128GP210A-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
100-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
7.37 MHz
Number Of Programmable I/os
85
Number Of Timers
13
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24HJ128GP210A-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC24HJ12GP201-ISO PDF datasheet
- PIC24HJ64GP206A-IMR PDF datasheet #2
- PIC24HJ64GP206A-IMR PDF datasheet #3
- Current page: 67 of 304
- Download datasheet (3Mb)
6.0
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESET Instruction
• WDT: Watchdog Timer Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Opcode and Uninitialized W
FIGURE 6-1:
2009 Microchip Technology Inc.
Register Reset
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
RESET
of the PIC24HJXXXGPX06A/X08A/X10A
family of devices. However, it is not
intended
reference source. To complement the
information in this data sheet, refer to
Section 8. “Reset” (DS70229) of the
“dsPIC33F/PIC24H Family Reference
Manual”, , which is available from the
Microchip website (www.microchip.com).
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
MCLR
V
DD
Uninitialized W Register
RESET SYSTEM BLOCK DIAGRAM
to
Regulator
RESET Instruction
Internal
Sleep or Idle
Illegal Opcode
be
Module
WDT
Trap Conflict
PIC24HJXXXGPX06A/X08A/X10A
a
comprehensive
V
DD
Detect
Glitch Filter
Rise
Preliminary
BOR
POR
A simplified block diagram of the Reset module is
shown in Figure 6-1.
Any active source of Reset will make the SYSRST sig-
nal active. Many registers associated with the CPU and
peripherals are forced to a known Reset state. Most
registers are unaffected by a Reset; their status is
unknown on POR and unchanged by all other Resets.
All types of device Reset will set a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1). A POR will clear all bits, except for
the POR bit (RCON<0>), that are set. The user can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
Note:
Note:
Refer to the specific peripheral or CPU
section of this manual for register Reset
states.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
SYSRST
DS70592B-page 67
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