DSPIC33FJ64GP706A-I/PT Microchip Technology, DSPIC33FJ64GP706A-I/PT Datasheet
DSPIC33FJ64GP706A-I/PT
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DSPIC33FJ64GP706A-I/PT Summary of contents
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... Microchip corporate web site (www.microchip.com). TABLE 1: SILICON DEVREV VALUES Part Number dsPIC33FJ64GP206A dsPIC33FJ64GP306A dsPIC33FJ64GP310A dsPIC33FJ64GP706A dsPIC33FJ64GP708A dsPIC33FJ64GP710A dsPIC33FJ128GP206A dsPIC33FJ128GP306A dsPIC33FJ128GP310A Note 1: The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. ...
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... PSV page. The EXCH instruction does not execute correctly. Writing to the SPIxBUF register as soon as TBF bit is cleared will cause SPI module to ignore written data. (2) Revision ID for Silicon Revision A3 A4 0x3009 0x300A Affected (1) Revisions devices, the © 2010 Microchip Technology Inc. ...
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... Operation Note 1: Only those issues indicated in the last column apply to the current silicon revision. © 2010 Microchip Technology Inc. Issue Summary ECAN module may not transmit Buffer 0 data if Buffer 1 data is queued for transmission first. The UART module will not generate back-to-back Break characters ...
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... Read mode and both of them transmit the data. The resultant data will be the ANDing of the two transmissions. Work around 2 In all I C devices, the addresses as well as bits A10 and A9 should be different. Affected Silicon Revisions devices on the bus, one of © 2010 Microchip Technology Inc. ...
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... Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. 9. Module: SPI In framed SPI mode, when the FRMDLY bit (SPIxCON2<1>) is cleared and the SMP bit (SPIxCON1<9>) is cleared, frame sync pulses do not get generated. Work around None. ...
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... Work around None. Affected Silicon Revisions 16. Module: I/O While device is being programmed via PGECx/ PGEDx pin pair, device pin with SDO1 functionality may start toggling. Work around None. Affected Silicon Revisions © 2010 Microchip Technology Inc. ...
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... X EXAMPLE 1: AD1CON1bits.ADON = 0; __asm__ volatile ("REPEAT #50"); __asm__ volatile ("NOP"); Sleep(); © 2010 Microchip Technology Inc. 18. Module: All The affected silicon revisions listed below are not warranted for operation at 150ºC. Work around Only use the affected revisions of silicon for Hi-Temp operating range from -40ºC to +140ºC. ...
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... T -40°C ≤ T Min Typ Max Units V — 0 — 0.8 SS 0.7 V — 5.5 DD 2.1 — 5.5 ≤ +85°C for Industrial A ≤+125°C for Extended A Conditions V SMBus disabled V SMBus enabled V SMBus disabled V SMBus enabled © 2010 Microchip Technology Inc. ...
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... Rev C Document (5/2010) Updated silicon issue 12 (CPU). Added silicon issue 17 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). Rev D Document (10/2010) Updated the work around in silicon issue 17 (ADC). Added silicon issue 18 (All). © 2010 Microchip Technology Inc C), (PSV DS80465D-page 9 ...
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... NOTES: DS80465D-page 10 © 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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