PIC16LF74-I/PT Microchip Technology, PIC16LF74-I/PT Datasheet - Page 103
![IC PIC MCU FLASH 4KX14 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC16LF74-I/PT
Manufacturer Part Number
PIC16LF74-I/PT
Description
IC PIC MCU FLASH 4KX14 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Specifications of PIC16LF74-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
PIC16LF74-I/PTR
PIC16LF74-I/PTR
PIC16LF74I/PT
PIC16LF74-I/PTR
PIC16LF74I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC16LF74-I/PT
Manufacturer:
MICROCHIPS
Quantity:
579
Company:
Part Number:
PIC16LF74-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16LF74-I/PTG
Manufacturer:
Microchip Technology
Quantity:
10 000
12.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit, WDTE (Section 12.1).
FIGURE 12-11:
TABLE 12-7:
2002 Microchip Technology Inc.
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Address
Note 1: See Register 12-1 for operation of these bits.
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
Config. bits
OPTION_REG
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
WATCHDOG TIMER BLOCK DIAGRAM
WDT Timer
Enable Bit
WDT
RBPU
From TMR0 Clock Source
(Figure 5-1)
Bit 7
(1)
BODEN
INTEDG
Bit 6
0
1
(1)
PSA
M
U
X
T0CS
Bit 5
—
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
T0SE
Bit 4
CP0
0
Note 1: The CLRWDT and SLEEP instructions
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
2: When a CLRWDT instruction is executed
PWRTE
1
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
Bit 3
PSA
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
8
(1)
PSA
To TMR0 (Figure 5-1)
WDTE
Bit 2
PS2
PS2:PS0
PIC16F7X
FOSC1
Bit 1
PS1
DS30325B-page 101
FOSC0
Bit 0
PS0