PIC16C72-10/SO Microchip Technology, PIC16C72-10/SO Datasheet - Page 70

• Manufacturer Part Number: PIC16C72-10/SO
• Description: IC MCU OTP 2KX14 A/D PWM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C72-10/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL309-1024 - ADAPTER 28-SOIC TO 28-DIP309-1023 - ADAPTER 28-SOIC TO 28-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC16C72 Series
10.12
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 10.1).
FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 10-13: SUMMARY OF WATCHDOG TIMER REGISTERS
DS39016A-page 70
Address
2007h
81h,181h
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 10-1 for operation of these bits.
Note: PSA and PS2:PS0 are bits in the OPTION register.
Watchdog Timer (WDT)
Name
Config. bits
OPTION
WDT Timer
Enable Bit
WDT
RBPU
Bit 7
From TMR0 Clock Source
(Figure 4-2)
(1)
BODEN
INTEDG
Bit 6
0
1
(1)
PSA
M
U
X
Preliminary
T0CS
Bit 5
CP1
T0SE
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
.
Bit 4
CP0
0
Note:
Note:
Time-out
8 - to - 1 MUX
MUX
WDT
Postscaler
PWRTE
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device RESET condition.
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
1
Bit 3
PSA
8
(1)
PSA
To TMR0 (Figure 4-2)
WDTE
Bit 2
PS2
1998 Microchip Technology Inc.
PS2:PS0
FOSC1
Bit 1
PS1
FOSC0
Bit 0
PS0