ATMEGA169P-16AU Atmel, ATMEGA169P-16AU Datasheet - Page 170
![IC AVR MCU 16K 16MHZ IND 64-TQFP](/photos/12/13/121332/313-64-tqfp_sml.jpg)
ATMEGA169P-16AU
Manufacturer Part Number
ATMEGA169P-16AU
Description
IC AVR MCU 16K 16MHZ IND 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169P-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI/USART/USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRBFLY
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Package
64TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
Operating Supply Voltage
3.3|5 V
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA169P-16AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 170 of 395
- Download datasheet (9Mb)
19.2.1
19.3
8018P–AVR–08/10
Clock Generation
AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
• Bit locations inside all USART Registers.
• Baud Rate Generation.
• Transmitter Operation.
• Transmit Buffer Functionality.
• Receiver Operation.
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
• A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO
• The Receiver Shift Register can now act as a third buffer level. This is done by allowing the
The following control bits have changed name, but have same functionality and register location:
• CHR9 is changed to UCSZn2.
• OR is changed to DORn.
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCK pin is only active when using synchronous mode.
Figure 19-2 on page 171
buffer. Therefore the UDRn must only be read once for each incoming data! More important is
the fact that the Error Flags (FEn and DORn) and the ninth data bit (RXB8n) are buffered with
the data in the receive buffer. Therefore the status bits must always be read before the UDRn
Register is read. Otherwise the error status will be lost since the buffer state is lost.
received data to remain in the serial Shift Register (see
Registers are full, until a new start bit is detected. The USART is therefore more resistant to
Data OverRun (DORn) error conditions.
shows a block diagram of the clock generation logic.
Figure 19-1 on page
ATmega169P
169) if the Buffer
170
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