PIC16LF84-04I/SO Microchip Technology, PIC16LF84-04I/SO Datasheet - Page 47

• Manufacturer Part Number: PIC16LF84-04I/SO
• Description: IC MCU FLASH 1KX14 EE 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF84-04I/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16LF
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 4MHz
• No. Of: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PIC16LC84A-04I/SO

8.11
The Watchdog Timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a '0' (Section 8.1).
8.11.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with
temperature, V
FIGURE 8-17: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-7
Address Name
2007h
81h
Legend: x = unknown. Shaded cells are not used by the WDT.
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
1997 Microchip Technology Inc.
Watchdog Timer (WDT)
WDT PERIOD
Config. bits
OPTION_
REG
DD
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
and process variations from part to
RBPU
Bit 7
WDT Timer
Enable Bit
—
WDT
INTEDG
Bit 6
From TMR0 Clock Source
(Figure 6-6)
—
•
T0CS
Bit 5
—
0
1
PSA
M
U
T0SE
X
Bit 4
CP
PWRTE
Bit 3
PSA
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT and
the postscaler (if assigned to the WDT) and prevent it
from
RESET condition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
8.11.2
It should also be taken into account that under worst
case conditions (V
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
0
Time-out
WDTE
MUX
8 - to -1 MUX
Bit 2
WDT
PS2
Postscaler
timing
WDT PROGRAMMING CONSIDERATIONS
•
1
8
FOSC1
Bit 1
PS1
out
DD
PSA
To TMR0 (Figure 6-6)
= Min., Temperature = Max., max.
FOSC0
and
Bit 0
PS0
PS2:PS0
PIC16C84
generating
1111 1111
Power-on
Value on
Reset
DS30445C-page 47
other resets
a
Value on all
1111 1111
device