PIC24HJ128GP504-I/ML Microchip Technology, PIC24HJ128GP504-I/ML Datasheet - Page 43

IC PIC MCU FLASH 128K 44QFN

PIC24HJ128GP504-I/ML

Manufacturer Part Number
PIC24HJ128GP504-I/ML
Description
IC PIC MCU FLASH 128K 44QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ128GP504-I/ML

Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Oscillator Type
Internal
Core Processor
PIC
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
8192Byte
Cpu Speed
40MHz
No. Of Timers
7
No.
RoHS Compliant
Embedded Interface Type
CAN, I2C, SPI, UART
Rohs Compliant
Yes
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
9
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 13 Channel
A/d Bit Size
12 bit
A/d Channels Available
13
Height
0.88 mm
Length
8 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
8 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDAC164336 - MODULE SOCKET FOR PM3 28/44QFNDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
Table 5-7
shows the ICSP programming details for
clearing the Configuration registers. In Step 1, the
Reset vector is exited. In Step 2, the write pointer (W7)
is loaded with 0x0000, which is the original destination
address (in TBLPAG, 0xF8 of program memory). In
Step 3, the NVMCON is set to program one
Configuration register. In Step 4, the TBLPAG register
is initialized to 0xF8 for writing to the Configuration
registers. In Step 5, the value to write to each
Configuration register is loaded to W0. In Step 6, the
Configuration register data is written to the write latch
using the TBLWTL instruction. In Steps 7 and 8, the
programming cycle is initiated. In Step 9, the internal
PC is set to 0x200 as a safety measure to prevent the
PC from incrementing into unimplemented memory.
Lastly, Steps 4-9 are repeated until all twelve
Configuration registers are written.
© 2010 Microchip Technology Inc.
DS70152H-page 43

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