PIC18LF4331-I/P Microchip Technology, PIC18LF4331-I/P Datasheet - Page 221
![IC PIC MCU FLASH 4KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4331-I/P
Manufacturer Part Number
PIC18LF4331-I/P
Description
IC PIC MCU FLASH 4KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
9.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18LF4331-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF4331-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18LF4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- PIC18F4331-EP PDF datasheet #9
- Current page: 221 of 392
- Download datasheet (4Mb)
20.2
The BRG is a dedicated 8-bit or 16-bit generator, that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode. Setting the BRG16 bit (BAUDCON<3>)
selects 16-bit mode.
The SPBRGH:SPBRG register pair controls the period
of a free-running timer. In Asynchronous mode, bits
BRGH (TXSTA<2>) and BRG16 also control the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 20-1
baud rate for different EUSART modes, which only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGH:SPBRG registers can be
calculated using the formulas in
the error in baud rate can be determined. An example
calculation is shown in
rates and error values for the various Asynchronous
modes
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG, to reduce the baud rate error or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGH:SPBRG registers
causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
TABLE 20-1:
2010 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair
SYNC
0
0
0
0
1
1
EUSART Baud Rate Generator
(BRG)
are
shows the formula for computation of the
Configuration Bits
shown
BAUD RATE FORMULAS
BRG16
0
0
1
1
0
1
in
Example
Table
Table
BRGH
20-2.
20-1. Typical baud
0
1
0
1
x
x
OSC
20-1. From this,
, the nearest
It
PIC18F2331/2431/4331/4431
may
BRG/EUSART Mode
be
16-Bit/Asynchronous
16-Bit/Asynchronous
16-Bit/Synchronous
8-Bit/Asynchronous
8-Bit/Asynchronous
8-Bit/Synchronous
20.2.1
The system clock is used to generate the desired baud
rate. However, when a power-managed mode is
entered, the clock source may be operating at a
different frequency than in PRI_RUN mode. In Sleep
mode, no clocks are present and in PRI_IDLE, the
primary clock source continues to provide clocks to the
Baud Rate Generator. However, in other power-
managed modes, the clock frequency will probably
change. This may require the value in SPBRG to be
adjusted.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit
and make sure that the receive operation is Idle before
changing the system clock.
20.2.2
The data on the RC7/RX/DT/SDO pin is sampled three
times by a majority detect circuit to determine if a high
or a low level is present at the RX pin.
POWER-MANAGED MODE
OPERATION
SAMPLING
Baud Rate Formula
F
F
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39616D-page 221
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