PIC16F767-I/ML Microchip Technology, PIC16F767-I/ML Datasheet - Page 174
![IC PIC MCU FLASH 8KX14 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC16F767-I/ML
Manufacturer Part Number
PIC16F767-I/ML
Description
IC PIC MCU FLASH 8KX14 28QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F737-ISP.pdf
(276 pages)
4.PIC16F737-ISP.pdf
(10 pages)
Specifications of PIC16F767-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3DBF777 - BOARD DAUGHTER ICEPIC3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F737-ISP PDF datasheet #3
- PIC16F737-ISP PDF datasheet #4
- Current page: 174 of 276
- Download datasheet (6Mb)
PIC16F7X7
15.2
The PIC16F7X7 differentiates between various kinds of
Reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• WDT Reset during normal operation
• WDT Wake-up during Sleep
• Brown-out Reset (BOR)
FIGURE 15-1:
DS30498C-page 172
Note 1:
MCLR/V
CLKI pin
OSC1/
V
PP
Reset
DD
This is the 32 kHz INTRC oscillator. See Section 4.0 “Oscillator Configurations” for more information.
/RE3 pin
INTRC
OST/PWRT
Brown-out
V
Module
DD
(1)
Detect
Detect
WDT
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Rise
OST
PWRT
10-bit Ripple Counter
WDT
Time-out
Reset
11-bit Ripple Counter
BORSEN
BOREN
Power-on Reset
External
Reset
Sleep
Some registers are not affected in any Reset condition.
Their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR Reset during Sleep and Brown-
out Reset (BOR). They are not affected by a WDT
wake-up which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared
differently in different Reset situations, as indicated in
Table 15-3. These bits are used in software to
determine the nature of the Reset. Upon a POR, BOR
or wake-up from Sleep, the CPU requires approxi-
mately 5-10 s to become ready for code execution.
This delay runs in parallel with any other timers. See
Table 15-4 for a full description of Reset states of all
registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 15-1.
Enable PWRT
Enable OST
2004 Microchip Technology Inc.
S
R
Q
Chip_Reset
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