PIC18F4431-I/P Microchip Technology, PIC18F4431-I/P Datasheet - Page 21

• Manufacturer Part Number: PIC18F4431-I/P
• Description: IC PIC MCU FLASH 8KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4431-I/P

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.0
4.1
Code memory is accessed one byte at a time via the
4-bit command, ‘1001’ (table read, post-increment).
The contents of memory pointed to by the table pointer
(TBLPTRU:TBLPTRH:TBLPTRL) are loaded into the
table latch and then serially output on SDATA.
TABLE 4-1:
FIGURE 4-1:
 2010 Microchip Technology Inc.
Step 1: Set table pointer.
Step 2: Read memory into table latch and then shift out on SDATA, LSb to MSb.
Command
SCLK
SDATA
0000
0000
0000
0000
0000
0000
1001
4-Bit
READING THE DEVICE
Read Code Memory, ID Locations,
and Configuration Bits
1
1
2
0
0E <Addr[21:16]>
6E F8
0E <Addr[15:8]>
6E F7
0E <Addr[7:0]>
6E F6
00 00
READ CODE MEMORY SEQUENCE
3
0
Data Payload
TABLE READ POST-INCREMENT INSTRUCTION TIMING (1001)
4
1
P5
SDATA = Input
1
2
3
4
MOVLW Addr[21:16]
MOVWF TBLPTRU
MOVLW <Addr[15:8]>
MOVWF TBLPTRH
MOVLW <Addr[7:0]>
MOVWF TBLPTRL
TBLRD *+
5
PIC18F2331/2431/4331/4431
6
7
8
P6
9
LSb
The 4-bit command is shifted in LSb first. The table
read is executed during the next 8 clocks, then shifted
out on SDATA during the last 8 clocks, LSb to MSb. A
delay of P6 must be introduced after the falling edge of
the 8th SCLK of the operand to allow SDATA to transi-
tion from an input to an output. During this time, SCLK
must be held low (see Figure 4-1). This operation also
increments the table pointer by one, pointing to the next
byte in code memory for the next read.
This technique will work to read any memory in the
000000h to 3FFFFFh address space, so it also applies
to the reading of the ID and Configuration registers.
P14
10
1
11
2
Core Instruction
SDATA = Output
Shift Data Out
12
3
13
4
14
5
15
6
16
MSb
P5A
Fetch Next 4-bit Command
1
SDATA = Input
n
2
DS30500B-page 21
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3
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4
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