DSPIC33FJ128GP202-E/SO Microchip Technology, DSPIC33FJ128GP202-E/SO Datasheet - Page 18
![IC DSPIC MCU/DSP 128K 28-SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
DSPIC33FJ128GP202-E/SO
Manufacturer Part Number
DSPIC33FJ128GP202-E/SO
Description
IC DSPIC MCU/DSP 128K 28-SOIC
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP202-E/SO
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 18 of 402
- Download datasheet (3Mb)
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1:
DS70292D-page 18
SCL1
SDA1
ASCL1
ASDA1
TMS
TCK
TDI
TDO
C1RX
C1TX
RTCC
CV
C1IN-
C1IN+
C1OUT
C2IN-
C2IN+
C2OUT
PMA0
PMA1
PMA2 -PMPA10
PMBE
PMCS1
PMD0-PMPD7
PMRD
PMWR
DAC1RN
DAC1RP
DAC1RM
DAC1LN
DAC1LP
DAC1LM
COFS
CSCK
CSDI
CSDO
PGWD1
PGEC1
PGWD2
PGEC2
PGWD3
PGEC3
MCLR
AV
Legend: CMOS = CMOS compatible input or output
DD
REF
Pin Name
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
PINOUT I/O DESCRIPTIONS (CONTINUED)
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/P
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
P
I
I
I
I
I
I
I
I
I
I
I
I
TTL/ST
TTL/ST
TTL/ST
Buffer
Type
ANA
ANA
ANA
ANA
ANA
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
PPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Synchronous serial clock input/output for I2C1.
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.
JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.
ECAN1 bus receive pin.
ECAN1 bus transmit pin.
Real-Time Clock Alarm Output.
Comparator Voltage Reference Output.
Comparator 1 Negative Input.
Comparator 1 Positive Input.
Comparator 1 Output.
Comparator 2 Negative Input.
Comparator 2 Positive Input.
Comparator 2 Output.
Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
Parallel Master Port Address (Demultiplexed Master Modes).
Parallel Master Port Byte Enable Strobe.
Parallel Master Port Chip Select 1 Strobe.
Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
DAC1 Right Channel Negative Output.
DAC1 Right Channel Positive Output.
DAC1 Right Channel Middle Point Value (typically 1.65V).
DAC1 Left Channel Negative Output.
DAC1 Left Channel Positive Output.
DAC1 Left Channel Middle Point Value (typically 1.65V).
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin
Data Converter Interface serial data output pin.
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
Master Clear (Reset) input. This pin is an active-low Reset to the
device.
Positive supply for analog modules. This pin must be connected at all
times.
Preliminary
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
Description
2009 Microchip Technology Inc.
P = Power
I = Input
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