PIC18F2525-I/SO Microchip Technology, PIC18F2525-I/SO Datasheet
PIC18F2525-I/SO
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PIC18F2525-I/SO Summary of contents
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... Device Data Sheet (DS39626), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2525/2620/4525/4620 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. The ...
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... PIC18F2525/2620/4525/4620 2. Module: MSSP When the MSSP is configured for SPI™ Master mode, the SDO pin cannot be disabled by setting the TRISC<5> bit. The SDO pin always outputs the content of SSPBUF regardless of the state of the TRIS bit. Work around Use Rev. A4 silicon devices. ...
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... None. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 8. Module: ECCP and CCP The CCP1 and CCP2 configured for PWM mode, with 1:1 Timer2 prescaler and duty cycle set to the period minus 1, may result in the PWM output(s) remaining at a logic low level ...
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... Increase system clock speed to 40 MHz and adjust A/D settings accordingly. Higher system clock frequencies decrease offset error. Date Codes that pertain to this issue: All engineering and production devices. TABLE 2: A/D CONVERTER CHARACTERISTICS: PIC18F2525/2620/4525/4620 (INDUSTRIAL) Param Symbol Characteristic No. A06A E Offset Error ...
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... T1CKPS1:T1CKPS0 bit values. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 15. Module: ECCP When a shutdown condition occurs, the output port(s) is made inactive for the duration of the event. After the event that caused the shutdown ...
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... PIC18F2525/2620/4525/4620 18. Module: EUSART When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTA register is set), the second byte may be corrupted written into TXREG immediately after the TMRT bit is set. Work around Execute a software delay, at least one half the transmission’s bit time, after TMRT is set and prior to writing subsequent bytes into TXREG ...
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... ISR code here : RETFIE FAST © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 Work around 1. Assembly Language Programming any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt. Instead, save/restore WREG, BSR and STATUS via software per Example 8-1 in the Device Data Sheet ...
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... PIC18F2525/2620/4525/4620 2. C Language Programming: The exact work around depends on the compiler in use. Please refer to your C compiler documentation for details. If using the Microchip MPLAB piler, define both high and low priority interrupt handler functions as “low priority” by using the pragma interruptlow directive. This direc- ...
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... Example 4. This example illustrates how it reduces the instruction cycle count from 10 cycles to 3: EXAMPLE 4: #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr void high_isr (void) { ... } © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS80200D-page 9 ...
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... PIC18F2525/2620/4525/4620 24. Module: EUSART The EUSART auto-baud feature may periodically measure the incoming baud rate incorrectly. The rate of incorrect baud rate measurements will depend on the frequency of the incoming synchronization byte and the system clock frequency. Work around None. Date Codes that pertain to this issue: All engineering and production devices ...
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... SSPOV bit is clear before disabling the module. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 33. Module: MSSP (SPI Mode) When the SPI is using Timer2/2 as the clock source, a shorter than expected SCK pulse may occur on the first bit of the transmitted/received data (Figure 1) ...
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... PIC18F2525/2620/4525/4620 34. Module: EUSART In rare situations, one or more extra zero bytes have been observed in a packet transmitted by the module operating in asynchronous mode. The actual data is not lost or corrupted; only unwanted (extra) zero bytes are observed in the packet. This situation has only been observed when the ...
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... Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 40. Module: MSSP In SPI mode, the SDO output may change after the inactive clock edge of the bit ‘0’ output. This may affect some SPI components that read data over 300 ns after the inactive edge of SCK ...
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... PIC18F2525/2620/4525/4620 42. Module: MSSP The MSSP configured for SPI mode, the Buffer Full Status bit, BF (SSPSTAT<0>) should not be polled in software to determine when the transfer is complete. Work around Copy the SSPSTAT register into a variable and perform the bit test on the variable. In Example 6, SSPSTAT is copied into the working register where the bit test is performed ...
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... Asynchronous Counter). Rev D Document (5/2006) Removed issue 34 (Timer1). Added Example 4 in issue 23 (Interrupts). Added issues 34-37 (EUSART), 38 (Timer1), 39-42 (MSSP), and 43 (Reset). Added Date Code information to new issues from revision C (issues 24-33). © 2006 Microchip Technology Inc. PIC18F2525/2620/4525/4620 DS80200D-page 15 ...
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... PIC18F2525/2620/4525/4620 NOTES: DS80200D-page 16 © 2006 Microchip Technology Inc. ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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