PIC16C73B-20/SS Microchip Technology, PIC16C73B-20/SS Datasheet - Page 97
![IC MCU OTP 4KX14 A/D PWM 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC16C73B-20/SS
Manufacturer Part Number
PIC16C73B-20/SS
Description
IC MCU OTP 4KX14 A/D PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C63A-04SP.pdf
(10 pages)
5.PIC16C63A-04SP.pdf
(10 pages)
Specifications of PIC16C73B-20/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
22
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
Controller Family/series
PIC16C
No. Of I/o's
22
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C73B-20/SS
Manufacturer:
GEA JAPAN
Quantity:
47
13.8
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the WDT will be cleared but keeps running,
the PD bit (STATUS<3>) is cleared, the TO (STA-
TUS<4>) bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP instruction was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V
cuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at V
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (V
13.8.1
The device can wake up from SLEEP through one of
the following events:
1.
2.
3.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
2000 Microchip Technology Inc.
External RESET input on MCLR pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
SSP (START/STOP) bit detect interrupt.
SSP transmit or receive in Slave mode
(SPI/I
CCP Capture mode interrupt.
Parallel Slave port read or write
(PIC16C65B/74B only).
A/D conversion (when A/D clock source is RC).
USART TX or RX (Synchronous Slave mode).
Power-down Mode (SLEEP)
2
C).
WAKE-UP FROM SLEEP
DD
or V
SS
, ensure no external cir-
DD
or V
SS
for lowest
IHMC
).
PIC16C63A/65B/73B/74B
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
13.8.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruc-
tion should be executed before a SLEEP instruction.
SLEEP instruction, the SLEEP instruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
tion of a SLEEP instruction, the device will imme-
diately wake up from sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
WAKE-UP USING INTERRUPTS
DS30605C-page 97