DSPIC33FJ128GP202-I/SP Microchip Technology, DSPIC33FJ128GP202-I/SP Datasheet - Page 164
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DSPIC33FJ128GP202-I/SP
Manufacturer Part Number
DSPIC33FJ128GP202-I/SP
Description
IC DSPIC MCU/DSP 128K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ128GP202-I/SP
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
8 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Package
28SPDIP
Device Core
dsPIC
Family Name
dsPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
On-chip Dac
2-chx16-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA330019 - PIM DSPIC33F MC 44P-100P QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ128GP202-I/SP
Manufacturer:
Microchip Technology
Quantity:
135
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 164 of 402
- Download datasheet (3Mb)
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
11.6.3
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
11.6.3.1
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the reg-
isters remain unchanged. To change these registers,
they must be unlocked in hardware. The register lock is
controlled by the IOLOCK bit (OSCCON<6>). Setting
IOLOCK prevents writes to the control registers;
clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1.
2.
3.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
DS70292D-page 164
Note:
Write 0x46 to OSCCON<7:0>.
Write 0x57 to OSCCON<7:0>.
Clear (or set) IOLOCK as a single operation.
CONTROLLING CONFIGURATION
CHANGES
MPLAB
functions for unlocking the OSCCON
register:
See MPLAB Help for more information.
Control Register Lock
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
®
C30 provides built-in C language
Preliminary
11.6.3.2
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset is
triggered.
11.6.3.3
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from being cleared after it has been set
once. If IOLOCK remains set, the register unlock
procedure does not execute, and the peripheral pin
select control registers cannot be written to. The only
way to clear the bit and re-enable peripheral remapping
is to perform a device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
Continuous State Monitoring
Configuration Bit Pin Select Lock
2009 Microchip Technology Inc.
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