PIC24HJ128GP202-I/SP Microchip Technology, PIC24HJ128GP202-I/SP Datasheet - Page 2
![IC PIC MCU FLASH 128K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC24HJ128GP202-I/SP
Manufacturer Part Number
PIC24HJ128GP202-I/SP
Description
IC PIC MCU FLASH 128K 28DIP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ128GP202-I/SP
Program Memory Type
FLASH
Program Memory Size
128KB (43K x 24)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM300027
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit or 10-ch x 12-bit
Controller Family/series
PIC24
No. Of I/o's
21
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
10. I
11. UART (UxE Interrupt)
12. UART Module
13. Comparator Module
14. Internal Voltage Regulator
15. Product Identification
16. PSV Operations
17. ECAN Module
18. ECAN Module
The following sections describe the errata and work
around to these errata, where they may apply.
DS80373B-page 2
The 10-bit slave does not set the RBF flag or load
the I2CxRCV register, on address match if the
Least Significant bits (LSbs) of the address are the
same as the 7-bit reserved addresses.
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
When the UART module is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
When
Comparator output pin cannot be used as a
General Purpose I/O pins even if the Comparator
is disabled.
When the VREGS (RCON<8>) bit is set to a logic
‘0’ higher sleep current may be observed.
Revision A2 devices marked as extended
temperature range (E) devices, support only
industrial temperature range (I).
An address error trap occurs in certain addressing
modes when accessing the first four bytes of any
PSV page.
The ECAN module may not store received data in
the correct location.
The ECAN module does not generate a CAN
event interrupt when coming out of Disable mode
on bus wake-up activity even if the WAKIE bit in
the CiINTE register is set.
2
C Module: 10-bit Addressing Mode
CMCON<CxOUTEN>
is
®
set,
encoder/
the
1. Module: UART
2. Module: UART
3. Module: SPI
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
When the UART is in 4x mode (BRGH = 1) and
using two Stop bits (STSEL = 1), it may sample the
first Stop bit instead of the second one.
This issue does not affect the other UART
configurations.
Work around
Use the 16x baud rate option (BRGH = 0) and
adjust the baud rate accordingly.
The SPI transmit buffer full (SPITBF) flag does not
get set immediately after writing to the buffer.
Work around
After a write to the SPI buffer, poll the SPITBF flag
until the flag gets set, indicating that the transmit
buffer is not full. Afterwards, poll the SPITBF flag
again until the flag gets cleared, indicating that the
transmit has started and that the transmit buffer is
empty and another write can occur.
© 2008 Microchip Technology Inc.