DSPIC33FJ64GP802-I/SP Microchip Technology, DSPIC33FJ64GP802-I/SP Datasheet - Page 266
![IC DSPIC MCU/DSP 64K 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
DSPIC33FJ64GP802-I/SP
Manufacturer Part Number
DSPIC33FJ64GP802-I/SP
Description
IC DSPIC MCU/DSP 64K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32GP204-IPT.pdf
(14 pages)
2.DSPIC33FJ32GP302-ISO.pdf
(412 pages)
3.DSPIC33FJ64GP804-IML.pdf
(402 pages)
Specifications of DSPIC33FJ64GP802-I/SP
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b, D/A 4x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
16 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ64GP802-I/SP
Manufacturer:
NIPPON
Quantity:
43 000
- DSPIC33FJ32GP204-IPT PDF datasheet
- DSPIC33FJ32GP302-ISO PDF datasheet #2
- DSPIC33FJ64GP804-IML PDF datasheet #3
- Current page: 266 of 412
- Download datasheet (6Mb)
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
22.4
The DAC clock signal clocks the internal logic of the
Audio DAC module. The data sample rate of the Audio
DAC is an integer division of the rate of the DAC clock.
The DAC clock is generated via a clock divider circuit
that accepts an auxiliary clock from the auxiliary
oscillator.
FIGURE 22-1:
FIGURE 22-2:
DS70292E-page 266
DAC Clock
CONTROL
Note: V
Note 1:
Count (DAC1RDAT)
Output (DAC1RN)
Output (DAC1RP)
OD
Negative DAC
Positive DAC
DAC input
+ = V
BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER
AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED)
If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register.
DACH
V
0x0000
0xFFFF
V
V
DACFDIV<6:0>
V
DACL
DACL
DACH
DACH
– V
DACL
V
V
DACM
ACLK
DACM
, V
OD
DAC1RDAT
DAC1LDAT
- = V
CLK DIV
DACL
– V
DACH
; refer to Audio DAC Module Specifications,
DACDFLT
The divisor ratio is programmed by clock divider bits
(DACFDIV<6:0>)
(DAC1CON). The resulting DAC clock must not exceed
25.6 MHz. If lower sample rates are to be used, then
the DAC filter clock frequency may be reduced to
reduce power consumption. The DAC clock frequency
is 256 times the sampling frequency.
Note 1
Note 1
D/A
D/A
in
© 2011 Microchip Technology Inc.
the
Amp
Amp
Table
DAC
30-46, for typical values.
Right Channel
Control
Left Channel
DAC1RM
DAC1RP
DAC1RN
DAC1LM
DAC1LP
DAC1LN
register
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