PIC18F87J60-I/PT Microchip Technology, PIC18F87J60-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F87J60-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J60-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 41.667MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 55
• Ram Size: 3808 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3808 B
• Interface Type: Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 41.667 MHz
• Number Of Programmable I/os: 55
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183033, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 15-ch x 10-bit
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 41.667 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5. Module: Ethernet (MIIM)
© 2008 Microchip Technology Inc.
When writing to any PHY register through the MIIM
interface’s MIWRL and MIWRH registers, the low
byte actually written to the PHY register may be
corrupted. The corruption occurs when the
following actions are taken:
• The application writes to MIWRL
• The PIC
• The application writes to MIWRH
For example, the following sequence will result in
a corrupted write to a PHY register:
In this example, 0xCF5 and 0xCF6 are GPR
memory locations that the application wishes to
write to the current PHY register defined by the
MIREGADR SFR. When the PIC MCU core
reads from
(‘b110011110110), the value originally written to
MIWRL will be corrupted.
Work around 1
Ensure that following a write to MIWRL, the firm-
ware does not access any of the problem memory
locations prior to writing to MIWRH. After finished
writing to MIWRH, normal operation can resume.
If interrupts are enabled, disable them prior to writ-
ing to MIWRL and MIWRH to prevent an Interrupt
Service Routine (ISR) from performing any reads
or writes to a problem memory address.
Special care must be taken to ensure that the
source data to be written to MIWRH does not
result in a problem memory access.
The following PHY write sequence avoids the
problem:
1. Copy the low byte, to be written to the PHY, into
2. Copy the high byte, to be written to the PHY,
3. Disable all interrupts by clearing GIEH and
4. Move PRODL into MIWRL.
5. Wait one instruction cycle, as required by the
6. Move PRODH into MIWRH.
7. Enable all interrupts that are needed by
that reads or writes to any memory address that
has the Least Significant six address bits of 36h
(‘b110110)
the PRODL register.
PRODL is at address FF3h and not subject to
the memory address issue.
into the PRODH register.
PRODH is at address FF4h and not subject to
the memory address issue.
GIEL in the INTCON register.
MAC host interface logic.
restoring GIEH and GIEL in INTCON.
MOVFF
NOP
MOVFF
®
MCU core executes any instruction
the
0xCF5, MIWRL
0xCF6, MIWRH
GPR
at
address
0xCF6
PIC18F97J60 FAMILY
6. Module: Ethernet (RX Filter)
Work around 2
If you cannot disable interrupts, as specified in
Work around 1, because the application cannot
tolerate interrupt latency variations:
• Perform the write (with interrupts enabled), but
• Verify the correct values were written by
If a corrupted value was written due to an interrupt
occurring, perform the write again and reverify.
The source data must be stored in a non-problem
location.
The application should follow the following
procedure:
1. Copy the low byte, to be written to the PHY, into
2. Copy the high byte, to be written to the PHY,
3. Move PRODL into MIWRL.
4. Wait one instruction cycle, as required by the
5. Move PRODH into MIWRH.
6. Wait two T
7. Perform a PHY register read of the same
8. Compare the read result with the original value
Date Codes that pertain to this issue:
All engineering and production devices.
When enabled, the Pattern Match receive filter
may allow some packets with an incorrect data
pattern to be received. Also, in certain configura-
tions, packets with a valid pattern may be
incorrectly discarded.
Work around
Do not use the Pattern Match hardware filter.
Instead, use the Unicast, Mutlicast, Broadcast and
Hash Table receive filters to accept all needed
packets and filter out unwanted ones in software.
Date Codes that pertain to this issue:
All engineering and production devices.
reading the PHY register
the PRODL register.
PRODL is at address FF3h and not subject to
the memory address issue.
into the PRODH register.
PRODH is at address FF4h and not subject to
the memory address issue.
MAC host interface logic.
(MISTAT<0>) until it is clear.
location.
copied to the PRODH:PRODL registers. If they
do not match, return to step 1.
CY
and then poll the BUSY bit
DS80292D-page 3