PIC24FJ128GA106-I/PT Microchip Technology, PIC24FJ128GA106-I/PT Datasheet - Page 133

• Manufacturer Part Number: PIC24FJ128GA106-I/PT
• Description: IC PIC MCU FLASH 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ128GA106-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (43K x 24)
• Package / Case: 64-TFQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 53
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDMA240015 - BOARD MCV PIM FOR 24F256GA
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.2
To compute the Baud Rate Generator reload value, use
the following equation:
EQUATION 15-1:
TABLE 15-1:
As a result of changes in the I2C protocol, several I2C
addresses are reserved and will not be acknowledged
in Slave mode.
TABLE 15-2:
© 2007 Microchip Technology Inc.
Legend: Shaded rows represent invalid reload values for a given F
Note 1:
Note 1:
Note 1: Based on F
I2CxBRG = (F
2:
3:
4:
2:
3:
Required
100 kHz
100 kHz
100 kHz
400 kHz
400 kHz
400 kHz
400 kHz
System
Setting Baud Rate When
Operating as a Bus Master
1 MHz
1 MHz
1 MHz
F
PLL are disabled.
SCL
Based on T
This is the closest value to 400 kHz for this value of F
F
I2CxBRG cannot have a value of less than 2.
Slave Address
The above address bits will not cause an address match, independent of address mask settings.
Address will be Acknowledged only if GCEN = 1.
Match on this address can only occur on the upper byte in 10-Bit Addressing mode.
CY
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
1111 1xx
1111 0xx
= 2 MHz is the minimum input clock frequency to have F
I
RESERVED I
2
CY
(1)
C™ CLOCK RATES
/F
CY
CY
SCL
= F
= T
– F
OSC
OSC
CY
16 MHz
16 MHz
16 MHz
/2; Doze mode and
8 MHz
4 MHz
8 MHz
4 MHz
2 MHz
8 MHz
4 MHz
2
/10,000,000) – 1
* 2
C™ ADDRESSES
F
CY
(2)
, Doze mode and PLL are disabled.
(1,3,4)
R/W Bit
PIC24FJ128GA010 FAMILY
0
1
x
x
x
x
x
x
Preliminary
(Decimal)
(1)
157
78
39
37
18
13
9
4
6
3
I2CxBRG Value
15.3
The I2CxMSK register (Register 15-3) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit loca-
tion (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding
address bit value is a ‘0’ or ‘1’. For example, when
I2CxMSK is set to ‘00100000’, the slave module will
detect both addresses ‘0000000’ and ‘00100000’.
To enable address masking, the IPMI (Intelligent
Peripheral Management Interface) must be disabled by
clearing the IPMIEN bit (I2CxCON<11>).
Address masking does not affect behavior. Refer to
Table 15-2 for a summary of these reserved addresses
.
CY
.
SCL
(Hexadecimal)
SCL
Slave Address Masking
and F
10-Bit Slave Upper Byte
9D
= 1 MHz.
4E
27
25
12
D
General Call Address
9
4
6
3
HS Mode Master Code
CY
.
C
Description
BUS
Start Byte
Reserved
Reserved
Reserved
Address
385 kHz
385 kHz
1,026 KHz
1,026 KHz
DS39747D-page 131
909 KHz
(2)
100 kHz
100 kHz
404 kHz
404 kHz
Actual
99 kHz
(3)
F
SCL
(2)
(2)