PIC18LF2431-I/SO Microchip Technology, PIC18LF2431-I/SO Datasheet - Page 286
![IC MCU FLASH 8KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18LF2431-I/SO
Manufacturer Part Number
PIC18LF2431-I/SO
Description
IC MCU FLASH 8KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16LF627A-IP.pdf
(8 pages)
3.PIC16F818-ISO.pdf
(6 pages)
4.PIC18F2331-ISO.pdf
(392 pages)
5.PIC18F2331-ISO.pdf
(8 pages)
6.PIC18F2331-ISO.pdf
(6 pages)
7.PIC18F2331-ISO.pdf
(16 pages)
8.PIC18LF2331-ISO.pdf
(4 pages)
9.PIC18LF2331-ISO.pdf
(40 pages)
10.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18LF2431-I/SO
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
PIC18
No. Of I/o's
24
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2431-I/SO
Manufacturer:
BOURNS
Quantity:
30 000
- PIC16F616T-ISL PDF datasheet
- PIC16LF627A-IP PDF datasheet #2
- PIC16F818-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18F2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- PIC18LF2331-ISO PDF datasheet #9
- PIC18F4331-EP PDF datasheet #10
- Current page: 286 of 400
- Download datasheet (7Mb)
PIC18F2331/2431/4331/4431
FIGURE 22-4:
22.4.3
As previously mentioned, entering a power-managed
mode clears the fail-safe condition. By entering a
power-managed mode, the clock multiplexer selects
the clock source selected by the OSCCON register.
Fail-safe monitoring of the power-managed clock
source resumes in the power-managed mode.
If an oscillator failure occurs during power-managed
operation, the subsequent events depend on whether
or not the oscillator failure interrupt is enabled. If
enabled (OSCFIF = 1), code execution will be clocked
by the INTOSC multiplexer. An automatic transition
back to the failed clock source will not occur.
If the interrupt is disabled, the device will not exit the
power-managed mode on oscillator failure. Instead, the
device will continue to operate as before, but clocked
by the INTOSC multiplexer. While in Idle mode, subse-
quent interrupts will cause the CPU to begin executing
instructions while being clocked by the INTOSC
multiplexer. The device will not transition to a different
clock source until the fail-safe condition is cleared.
DS39616C-page 284
Note:
Sample Clock
CM Output
FSCM INTERRUPTS IN
POWER-MANAGED MODES
OSCFIF
System
Output
Clock
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
FSCM TIMING DIAGRAM
CM Test
Preliminary
22.4.4
The FSCM is designed to detect oscillator failure at any
point after the device has exited Power-on Reset
(POR) or low-power Sleep mode. When the primary
system clock is EC, RC or INTRC modes, monitoring
can begin immediately following these events.
For oscillator modes involving a crystal or resonator
(HS, HSPLL, LP or XT), the situation is somewhat
different. Since the oscillator may require a start-up
time considerably longer than the FCSM sample clock
time, a false clock failure may be detected. To prevent
this, the internal oscillator block is automatically
configured as the system clock and functions until the
primary clock is stable (the OST and PLL timers have
timed out). This is identical to Two-Speed Start-up
mode. Once the primary clock is stable, the INTRC
returns to its role as the FSCM source.
As noted in Section 22.3.1 “Special Considerations
for Using Two-Speed Start-up”, it is also possible to
select another clock configuration and enter an
alternate power-managed mode, while waiting for the
primary system clock to become stable. When the new
powered-managed mode is selected, the primary clock
is disabled.
Note:
CM Test
Oscillator
Failure
POR OR WAKE FROM SLEEP
The same logic that prevents false
oscillator failure interrupts on POR or wake
from Sleep will also prevent the detection of
the oscillator’s failure to start at all following
these events. This can be avoided by
monitoring the OSTS bit and using a timing
routine to determine if the oscillator is
taking too long to start. Even so, no
oscillator failure interrupt will be flagged.
© 2007 Microchip Technology Inc.
Detected
Failure
CM Test
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