PIC16LF84A-04I/SS Microchip Technology, PIC16LF84A-04I/SS Datasheet - Page 30

• Manufacturer Part Number: PIC16LF84A-04I/SS
• Description: IC MCU FLASH 1KX14 EE 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF84A-04I/SS

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC16LF
• No. Of I/o's: 13
• Eeprom Memory Size: 64Byte
• Ram Memory Size: 68Byte
• Cpu Speed: 4MHz
• No. Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F84A
FIGURE 6-9:
6.7
On power-up (Figures 6-6 through 6-9), the time-out
sequence is as follows:
1.
2.
The total time-out will vary based on oscillator configu-
ration and PWRTE configuration bit status. For exam-
ple, in RC mode with the PWRT disabled, there will be
no time-out at all.
TABLE 6-5:
DS35007B-page 28
Configuration
XT, HS, LP
Oscillator
INTERNAL RESET
PWRT time-out is invoked after a POR has
expired.
Then, the OST is activated.
PWRT TIME-OUT
INTERNAL POR
OST TIME-OUT
RC
Time-out Sequence and
Power-down Status Bits (TO/PD)
When V
has reached its final value. In this example, the chip will reset properly if, and only if, V1
MCLR
V
1024T
TIME-OUT IN VARIOUS
SITUATIONS
DD
Enabled
72 ms +
PWRT
DD
72 ms
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
SLOW V
rises very slowly, it is possible that the T
Power-up
OSC
1024T
Disabled
PWRT
DD
—
RISE TIME
OSC
1024T
Wake-up
SLEEP
from
—
OSC
PWRT
T
PWRT
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high, execution will begin immediately
(Figure 6-6). This is useful for testing purposes or to
synchronize more than one PIC16F84A device when
operating in parallel.
Table 6-6 shows the significance of the TO and PD bits.
Table 6-3 lists the RESET conditions for some special
registers, while Table 6-4 lists the RESET conditions
for all the registers.
TABLE 6-6:
time-out and T
TO
1
0
x
0
0
1
1
PD
1
x
0
1
0
1
0
OST
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset (during normal operation)
WDT Wake-up
MCLR during normal operation
MCLR during SLEEP or interrupt
wake-up from SLEEP
time-out will expire before V
STATUS BITS AND THEIR
SIGNIFICANCE
T
OST
V1
2001 Microchip Technology Inc.
DD
Condition
V
):
DD
min.
DD