PIC32MX420F032H-40I/MR Microchip Technology, PIC32MX420F032H-40I/MR Datasheet - Page 52
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PIC32MX420F032H-40I/MR
Manufacturer Part Number
PIC32MX420F032H-40I/MR
Description
IC PIC MCU FLASH 32KX32 64-QFN
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX420F032H-40I/MR
Core Size
32-Bit
Program Memory Size
32KB (32K x 8)
Core Processor
MIPS32® M4K™
Speed
40MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VFQFN, Exposed Pad
Controller Family/series
PIC32
Ram Memory Size
8KB
Cpu Speed
40MHz
No. Of Timers
5
Interface
EUSART, I2C, SPI, USB
No. Of Pwm Channels
5
Embedded Interface Type
EUSART, I2C, SPI, USB
Rohs Compliant
Yes
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, JTAG, SPI, TWI, UART, USB
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
51
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / Rohs Status
Details
PIC32MX
18.1
In PIC32MX devices, the Configuration Words select
various device configurations. These Configuration
Words are implemented as volatile memory registers
and must be loaded from the nonvolatile programmed
Configuration data mapped in the last four words
(32-bit x 4 words) of boot Flash memory, DEVCFG0-
DEVCFG3. These are the four locations an external
programming device programs with the appropriate
Configuration data (see Table 18-3).
TABLE 18-3:
On Power-on Reset (POR), or any Reset, the Configu-
ration Words are copied from the boot Flash memory to
their corresponding Configuration registers. A Configu-
ration bit can only be programmed = 0 (unprogrammed
state = 1).
During programming, a Configuration Word can be pro-
grammed a maximum of two times before a page erase
must be performed.
After programming the Configuration Words, the device
must be reset to ensure that the Configuration registers
are reloaded with the new programmed data.
18.1.1
To prevent inadvertent Configuration bit changes dur-
ing code execution, all programmable Configuration
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again.
Changing a device configuration requires changing the
Configuration data in the boot Flash memory, and
cycling power to the device.
To ensure integrity of the 128-bit data, a comparison is
made between each Configuration bit and its stored
complement continuously. If a mismatch is detected, a
Configuration Mismatch Reset is generated, which
causes a device Reset.
DS61145G-page 52
Configuration Word
Device Configuration
DEVCFG0
DEVCFG1
DEVCFG2
DEVCFG3
CONFIGURATION REGISTER
PROTECTION
DEVCFG LOCATIONS
0xBFC0_2FFC
0xBFC0_2FF8
0xBFC0_2FF4
0xBFC0_2FF0
Address
18.2
The PIC32MX features a single device Code-Protec-
tion bit (CP). CP, when programmed = 0, protects boot
Flash and program Flash from being read or modified
by an external programming device. When code-
protection is enabled, only the Device ID and User ID
registers are available to be read by an external
programmer. However, Boot Flash and program Flash
memory are not protected from self-programming
during program execution when code-protection is
enabled.
18.3
In addition to a device Code-Protection bit, the PIC32MX
also features Program Write-Protection bits (PWP) to
prevent boot Flash and program Flash memory regions
from being written during code execution.
Boot Flash memory is write-protected with a single
Configuration bit, BWP (DEVCFG0<24>), when
programmed = 0.
Program Flash memory can be write-protected entirely
or in selectable page sizes using Configuration bits
PWP<7:0> (BCFG0<19:12>). A page of program Flash
memory is 4096 bytes (1024 words). The PWP bits rep-
resent the 1’s complement of the number of protected
pages. For example, programming PWP bits = 0xFF
selects 0 pages to be write-protected, effectively dis-
abling the program Flash write protection. Program-
ming PWP bits = 0xFE selects the first page to be write-
protected. When enabled, the write-protected memory
range is inclusive from the beginning of program Flash
memory (0xBD00_0000) up through the selected page.
Refer to Table 18-4 for specific write-protection ranges.
The amount of program Flash memory available for
write protection depends on the family device variant.
Note:
Device Code-Protection Bit (CP)
Program Write-Protection Bits
(PWP)
The PWP bits represent the 1’s complement
of the number of protected pages.
© 2010 Microchip Technology Inc.