PIC18F2455-I/SO Microchip Technology, PIC18F2455-I/SO Datasheet - Page 125
![IC PIC MCU FLASH 12KX16 28SOIC](/photos/6/59/65909/150-28-soic_sml.jpg)
PIC18F2455-I/SO
Manufacturer Part Number
PIC18F2455-I/SO
Description
IC PIC MCU FLASH 12KX16 28SOIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
7.PIC18F2455-ISO.pdf
(426 pages)
8.PIC18LF2455-ISO.pdf
(430 pages)
Specifications of PIC18F2455-I/SO
Program Memory Type
FLASH
Program Memory Size
24KB (12K x 16)
Package / Case
28-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI/I2C/EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10-ch x 10-bit
Package
28SOIC W
Device Core
PIC
Family Name
PIC18
Maximum Speed
48 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4550 - BOARD DAUGHTER ICEPIC3DM163025 - PIC DEM FULL SPEED USB DEMO BRD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2455-I/SO
Manufacturer:
Microchi
Quantity:
4 052
Part Number:
PIC18F2455-I/SO
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- PIC18F2455-ISO PDF datasheet #7
- PIC18LF2455-ISO PDF datasheet #8
- Current page: 125 of 426
- Download datasheet (8Mb)
10.5
Depending on the particular PIC18F2455/2550/4455/
4550 device selected, PORTE is implemented in two
different ways.
For 40/44-pin devices, PORTE is a 4-bit wide port.
Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP
and RE2/AN7/OESPP) are individually configurable as
inputs or outputs. These pins have Schmitt Trigger
input buffers. When selected as an analog input, these
pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a high-impedance mode). Clearing a TRISE bit
(= 0) will make the corresponding PORTE pin an output
(i.e., put the contents of the output latch on the selected
pin).
In addition to port data, the PORTE register
(Register 10-1) also contains the RDPU control bit
(PORTE<7>); this enables or disables the weak
pull-ups on PORTD.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
REGISTER 10-1:
2004 Microchip Technology Inc.
Note:
PORTE, TRISE and LATE
Registers
bit 7
bit 6-4
bit 3-0
On a Power-on Reset, RE2:RE0 are
configured as analog inputs.
PORTE REGISTER
RDPU: PORTD Pull-up Enable bit
1 = PORTD pull-ups are enabled by individual port latch values
0 = All PORTD pull-ups are disabled
Unimplemented: Read as ‘0’
RE3:RE0: PORTE Data Input bits
bit 7
Legend:
R = Readable bit
-n = Value at POR
RDPU
Note 1: Implemented only when Master Clear functionality is disabled (MCLRE
R-0
(3)
2: RE3 is the only PORTE bit implemented on both 28-pin and 40/44-pin devices. All
3: Unimplemented in 28-pin devices; read as ‘0’.
configuration bit = 0); otherwise, read as ‘0’.
other bits are implemented only when PORTE is implemented (i.e., 40/44-pin devices).
U-0
—
PIC18F2455/2550/4455/4550
U-0
Preliminary
—
W = Writable bit
‘1’ = Bit is set
(1,2)
U-0
—
The fourth pin of PORTE (MCLR/V
only pin. Its operation is controlled by the MCLRE
configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with
its operation. Otherwise, it functions as the device’s Mas-
ter Clear input. In either configuration, RE3 also functions
as the programming voltage input during programming.
EXAMPLE 10-5:
10.5.1
For 28-pin devices, PORTE is only available when
Master Clear functionality is disabled (MCLRE = 0). In
these cases, PORTE is a single bit, input only port
comprised of RE3 only. The pin operates as previously
described.
CLRF
CLRF
MOVLW
MOVWF
MOVLW
MOVLW
MOVWF
MOVWF
Note:
RE3
R/W-1
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PORTE
LATE
0Ah
ADCON1 ; for digital inputs
03h
07h
CMCON
TRISC
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
PORTE IN 28-PIN DEVICES
(1,2)
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure A/D
; Value used to
; initialize data
; direction
; Turn off
; comparators
; Set RE<0> as inputs
; RE<1> as outputs
; RE<2> as inputs
RE2
R/W-1
INITIALIZING PORTE
(3)
x = Bit is unknown
RE1
R/W-1
PP
DS39632B-page 123
/RE3) is an input
(3)
RE0
R/W-1
bit 0
(3)
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