DSPIC33FJ32MC304-E/PT Microchip Technology, DSPIC33FJ32MC304-E/PT Datasheet - Page 89
![IC DSPIC MCU/DSP 32K 44-TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
DSPIC33FJ32MC304-E/PT
Manufacturer Part Number
DSPIC33FJ32MC304-E/PT
Description
IC DSPIC MCU/DSP 32K 44-TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ32MC202-IMM.pdf
(14 pages)
2.DSPIC33FJ32MC302-ISO.pdf
(436 pages)
3.DSPIC33FJ64MC202-ESO.pdf
(424 pages)
Specifications of DSPIC33FJ32MC304-E/PT
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
44-TQFP, 44-VQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
35
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 9x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Data Ram Size
4 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330018
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ32MC304-E/PT
Manufacturer:
Microchip
Quantity:
225
Company:
Part Number:
DSPIC33FJ32MC304-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ32MC202-IMM PDF datasheet
- DSPIC33FJ32MC302-ISO PDF datasheet #2
- DSPIC33FJ64MC202-ESO PDF datasheet #3
- Current page: 89 of 436
- Download datasheet (6Mb)
FIGURE 6-3:
6.3
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse width will generate a Reset. Refer
to
minimum pulse width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.3.0.1
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.3.0.2
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to V
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
6.4
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a
special Reset state. This Reset state will not re-
initialize the clock. The clock source in effect prior to the
RESET instruction will remain. SYSRST is released at
the next instruction cycle, and the reset vector fetch will
commence.
© 2011 Microchip Technology Inc.
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
Section 31.0 “Electrical Characteristics”
SYSRST
SYSRST
SYSRST
External Reset (EXTR)
Software RESET Instruction (SWR)
V
V
V
DD
DD
DD
EXTERNAL SUPERVISORY CIRCUIT
INTERNAL SUPERVISORY CIRCUIT
V
DD
dips before PWRT expires
BROWN-OUT SITUATIONS
DD
. In this case, the
for
T
BOR
+ T
T
T
PWRT
BOR
BOR
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control register (RCON<6>) is set to indicate
the software Reset.
6.5
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
The Watchdog Timer Time-out Flag bit (WDTO) in the
Reset Control register (RCON<4>) is set to indicate
the
“Watchdog Timer (WDT)”
Watchdog Reset.
6.6
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
The Trap Reset Flag bit (TRAPR) in the Reset Control
register (RCON<15>) is set to indicate the Trap Conflict
Reset. Refer to
more information on trap conflict Resets.
+ T
+ T
PWRT
PWRT
Watchdog
Watchdog Time-out Reset (WDTO)
Trap Conflict Reset
Section 7.0 “Interrupt Controller”
Reset.
Refer
V
V
for more information on
V
BOR
BOR
BOR
to
DS70291E-page 89
Section 28.4
for
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