PIC24HJ64GP206-I/PT Microchip Technology, PIC24HJ64GP206-I/PT Datasheet - Page 68
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC24HJ64GP206-I/PT
Manufacturer Part Number
PIC24HJ64GP206-I/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ64GP206-IPT.pdf
(292 pages)
3.PIC24HJ64GP206-IPT.pdf
(8 pages)
4.PIC24HJ64GP206-IPT.pdf
(20 pages)
5.PIC24HJ64GP206-IPT.pdf
(26 pages)
6.PIC24HJ128GP206-IPT.pdf
(286 pages)
7.PIC24HJ128GP306-IPT.pdf
(288 pages)
Specifications of PIC24HJ64GP206-I/PT
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 18x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
CAN, I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
13
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 18 Channel
Controller Family/series
PIC24
No. Of I/o's
53
Ram Memory Size
8KB
Cpu Speed
40MIPS
No. Of Timers
13
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Height
1 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM300024 - KIT DEMO DSPICDEM 1.1MA240012 - MODULE PLUG-IN PIC24H 100QFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM300019 - BOARD DEMO DSPICDEM 80L STARTERDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC24HJ64GP206-I/PT
Manufacturer:
Microchi
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297
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PIC24HJ64GP206-I/PT
Manufacturer:
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PIC24HJXXXGPX06/X08/X10
TABLE 6-3:
6.2.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) have a relatively long start-up
time. Therefore, one or more of the following conditions
is possible after the Reset signal is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
6.2.2
If the FSCM is enabled, it begins to monitor the system
clock source when the Reset signal is released. If a
valid clock source is not available at this time, the
device automatically switches to the FRC oscillator and
the user can switch to the desired crystal oscillator in
the Trap Service Routine.
DS70175H-page 66
POR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
2:
3:
4:
5:
6:
T
T
Power-up Timer delay (if regulator is disabled). T
states, including waking from Sleep mode, only if the regulator is enabled.
T
T
oscillator clock to the system.
T
T
POR AND LONG OSCILLATOR
START-UP TIMES
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
STARTUP
OST
POR
RST
LOCK
FSCM
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
= Internal state Reset time (20 μs nominal).
= Power-on Reset delay (10 μs nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time (20 μs nominal).
= Fail-Safe Clock Monitor delay (100 μs nominal).
EC, FRC, LPRC
ECPLL, FRCPLL
XT, HS, SOSC
XTPLL, HSPLL
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
Clock Source
= Conditional POR delay of 20 μs nominal (if on-chip regulator is enabled) or 64 ms nominal
T
T
T
T
POR
POR
POR
POR
SYSRST Delay
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
STARTUP
+ T
+ T
+ T
+ T
6.2.2.1
When the system clock source is provided by a crystal
oscillator and/or the PLL, a small delay, T
matically inserted after the POR and PWRT delay
times. The FSCM does not begin to monitor the system
clock source until this delay expires. The FSCM delay
time is nominally 500 μs and provides additional time
for the oscillator and/or PLL to stabilize. In most cases,
the FSCM delay prevents an oscillator failure trap at a
device Reset when the PWRT is disabled.
6.3
Most of the Special Function Registers (SFRs) associ-
ated with the CPU and peripherals are reset to a
particular value at a device Reset. The SFRs are
grouped by their peripheral or CPU function and their
Reset values are specified in each section of this
manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of two registers. The
Reset value for the Reset Control register, RCON,
depends on the type of device Reset. The Reset value
for the Oscillator Control register, OSCCON, depends
on the type of Reset and the programmed values of the
oscillator Configuration bits in the FOSC Configuration
register.
RST
RST
RST
RST
is also applied to all returns from powered-down
Special Function Register Reset
States
System Clock
T
OST
FSCM Delay for Crystal and PLL
Clock Sources
T
Delay
T
LOCK
+ T
OST
—
—
—
—
—
—
—
LOCK
© 2009 Microchip Technology Inc.
FSCM
T
T
T
Delay
FSCM
FSCM
FSCM
—
—
—
—
—
—
—
1, 2, 3
1, 2, 3, 5, 6
1, 2, 3, 4, 6
1, 2, 3, 4, 5, 6
3
3
3
3
3
3
FSCM
Notes
, is auto-