PIC24HJ64GP204-I/ML Microchip Technology, PIC24HJ64GP204-I/ML Datasheet - Page 3
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PIC24HJ64GP204-I/ML
Manufacturer Part Number
PIC24HJ64GP204-I/ML
Description
IC PIC MCU FLASH 64K 44-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(84 pages)
2.PIC24HJ32GP302-ISO.pdf
(368 pages)
3.PIC24HJ32GP302-ISO.pdf
(8 pages)
4.PIC24HJ32GP302-ISO.pdf
(12 pages)
5.PIC24HJ32GP304-EML.pdf
(356 pages)
Specifications of PIC24HJ64GP204-I/ML
Program Memory Type
FLASH
Program Memory Size
64KB (22K x 24)
Package / Case
44-QFN
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
35
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
35
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel / 12 bit, 13 Channel
Controller Family/series
PIC24
No. Of I/o's
35
Ram Memory Size
4KB
Cpu Speed
40MIPS
No. Of Timers
7
Embedded Interface Type
I2C, SPI, UART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
2.4
The program memory map extends from 0x0 to
0xFFFFFE. Code storage is located at the base of the
memory map and supports up to 88K instructions
(about 256 Kbytes).
memory size and number of erase and program blocks
present in each device variant. Each erase block or
page contains 512 instructions and each program block
or row, contains 64 instructions.
Locations 0x800000 through 0x800FFE are reserved
for executive code memory. This region stores the
programming
executive. The programming executive is used for
TABLE 2-2:
© 2010 Microchip Technology Inc.
dsPIC33FJ06GS101
dsPIC33FJ06GS102
dsPIC33FJ06GS202
dsPIC33FJ16GS402
dsPIC33FJ16GS404
dsPIC33FJ16GS502
dsPIC33FJ16GS504
dsPIC33FJ12GP201
dsPIC33FJ12GP202
dsPIC33FJ16GP304
dsPIC33FJ32GP202
dsPIC33FJ32GP204
dsPIC33FJ32GP302
dsPIC33FJ32GP304
dsPIC33FJ64GP202
dsPIC33FJ64GP204
dsPIC33FJ64GP206
dsPIC33FJ64GP306
dsPIC33FJ64GP310
dsPIC33FJ64GP706
dsPIC33FJ64GP708
dsPIC33FJ64GP710
dsPIC33FJ64GP802
dsPIC33FJ64GP804
dsPIC33FJ128GP202
dsPIC33FJ128GP204
dsPIC33FJ128GP206
dsPIC33FJ128GP306
dsPIC33FJ128GP310
dsPIC33FJ128GP706
dsPIC33FJ128GP708
dsPIC33F/PIC24H Device
Memory Map
executive
CODE MEMORY SIZE
Table 2-2
User Memory Address
and
(Instruction Words)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x00ABFE (22K)
0x0057FE (11K)
0x0057FE (11K)
0x0057FE (11K)
0x0057FE (11K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
0x0157FE (44K)
shows the program
0x002BFE (6K)
0x002BFE (6K)
0x002BFE (6K)
0x002BFE (6K)
0x002BFE (6K)
0x000FFE (2K)
0x000FFE (2K)
0x000FFE (2K)
0x001FFE (4K)
0x001FFE (4K)
the
Limit
debugging
Write Blocks
176
176
176
176
344
344
344
344
344
344
344
344
344
344
688
688
688
688
688
688
688
32
32
32
88
88
88
88
64
64
88
device programming and the debug executive is
used for in-circuit debugging. This region of memory
cannot be used to store user code.
Locations 0xF80000 through 0xF80017 are reserved
for the device Configuration registers.
Locations 0xFF0000 and 0xFF0002 are reserved for
the Device ID Word registers. These bits can be used
by the programmer to identify which device type is
being programmed. They are described in
“Device
normally, even after code protection is applied.
Figure 2-3
dsPIC33F/PIC24H family variants.
ID”. The Device ID registers read out
Erase Blocks
illustrates the memory map for the
22
22
22
22
43
43
43
43
43
43
43
43
43
43
86
86
86
86
86
86
86
11
11
11
11
11
4
4
4
8
8
(Instruction Words)
Executive Memory
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
0x800FFE (2K)
Address Limit
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
0x8007FE (1K)
DS70152H-page 3
Section 7.0