PIC18F67J60-I/PT Microchip Technology, PIC18F67J60-I/PT Datasheet - Page 243
![IC PIC MCU FLASH 64KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F67J60-I/PT
Manufacturer Part Number
PIC18F67J60-I/PT
Description
IC PIC MCU FLASH 64KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
5.PIC18F97J60-IPT.pdf
(476 pages)
Specifications of PIC18F67J60-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
39
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver/Ethernet/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
39
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM183033 - BOARD DEMO INTERNET RADIOAC162064 - HEADER INTFC MPLABICD2 64/80/100AC164327 - MODULE SKT FOR 64TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F67J60-I/PT
Manufacturer:
SEMTECH
Quantity:
1 001
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Part Number:
PIC18F67J60-I/PT
Manufacturer:
Microchip Technology
Quantity:
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20 000
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- PIC18F97J60-IPT PDF datasheet #5
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- Download datasheet (8Mb)
TABLE 18-5:
18.5.3.2
To process the packet, an application will normally start
reading from the beginning of the Next Packet Pointer.
The application will save the Next Packet Pointer, any
necessary bytes from the receive status vector, and
then proceed to read the actual packet contents. If the
AUTOINC bit is set, it will be able to sequentially read
the entire packet without ever modifying the ERDPT
registers. The Read Pointer would automatically wrap
at the end of the circular receive buffer to the beginning.
EQUATION 18-1:
© 2009 Microchip Technology Inc.
If Packet Start Address + Offset > ERXND, then
else
15-0
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Zero
Receive VLAN Type Detected
Receive Unknown Opcode
Receive Pause Control Frame
Receive Control Frame
Dribble Nibble
Receive Broadcast Packet
Receive Multicast Packet
Received OK
Length Out of Range
Length Check Error
CRC Error
Reserved
Carrier Event Previously Seen
Reserved
Long Event/Drop Event
Received Byte Count
Reading Received Packets
ERDPT = Packet Start Address + Offset – (ERXND – ERXST + 1)
ERDPT = Packet Start Address + Offset
RECEIVE STATUS VECTORS
RANDOM ACCESS ADDRESS CALCULATION
Field
‘0’
Current frame was recognized as a VLAN tagged frame.
Current frame was recognized as a control frame but it contained an
unknown opcode.
Current frame was recognized as a control frame containing a valid pause
frame opcode and a valid destination address.
Current frame was recognized as a control frame for having a valid
type/length designating it as a control frame.
Indicates that after the end of this packet, an additional 1 to 7 bits were
received. The extra bits were thrown away.
Indicates packet received had a valid Broadcast address.
Indicates packet received had a valid Multicast address.
Indicates that the packet had a valid CRC and no symbol errors.
Indicates that frame type/length field was larger than 1500 bytes
(type field).
Indicates that frame length field value in the packet does not match the
actual data byte length.
Indicates that the frame CRC field value does not match the CRC
calculated by the MAC.
Indicates that at some time since the last receive, a carrier event was
detected. The carrier event is not associated with this packet. A carrier
event is activity on the receive channel that does not result in a packet
receive attempt being made.
Indicates a packet over 50,000 bit times occurred or that a packet was
dropped since the last receive.
Indicates length of the received frame. This includes the destination
address, source address, type/length, data, padding and CRC fields. This
field is stored in little-endian format.
PIC18F97J60 FAMILY
In the event that the application needed to randomly
access the packet, it would be necessary to manually
calculate the proper ERDPT registers, taking care to
not exceed the end of the receive buffer, if the packet
spans the ERXND to ERXST buffer boundary. In other
words, given the packet start address and a desired
offset, the application should follow the logic shown in
Equation 18-1.
Description
DS39762E-page 243
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