DSPIC33FJ32MC302-E/MM Microchip Technology, DSPIC33FJ32MC302-E/MM Datasheet
DSPIC33FJ32MC302-E/MM
Specifications of DSPIC33FJ32MC302-E/MM
Related parts for DSPIC33FJ32MC302-E/MM
DSPIC33FJ32MC302-E/MM Summary of contents
Page 1
... Microchip Technology Inc. dsPIC33FJ32MC302/304, High-Performance, 16-bit Digital Signal Controllers Preliminary Data Sheet DS70291D ...
Page 2
... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 3
... RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA © 2009 Microchip Technology Inc. dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 Timers/Capture/Compare/PWM: • Timer/Counters five 16-bit timers: - Can pair up to make two 32-bit timers - One timer runs as a Real-Time Clock with an external 32 ...
Page 4
... Encoder Interface module: - Phase A, Phase B, and index pulse input - 16-bit up/down position counter - Count direction status - Position Measurement (x2 and x4) mode - Programmable digital noise filters on inputs - Alternate 16-bit Timer/Counter mode - Interrupt on position counter rollover/underflow Preliminary © 2009 Microchip Technology Inc. ...
Page 5
... Programmable Cyclic Redundancy Check (CRC): - Programmable bit length for the CRC generator polynomial (up to 16-bit length) - 8-deep, 16-bit or 16-deep, 8-bit FIFO for data input © 2009 Microchip Technology Inc. Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See the device variant table for exact peripheral features per device ...
Page 6
... Note 1: RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32MC302/304, which include 1 Kbyte of DMA RAM. 2: Only four out of five timers are remappable. 3: Only PWM fault pins are remappable. 4: Only two out of three interrupts are remappable. DS70291D-page 6 Remappable Peripheral ...
Page 7
... OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © ...
Page 8
... SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V ...
Page 9
... SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Controller Families” in this section for the list of available peripherals. 2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to V © ...
Page 10
... REF OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Controller Families” in this section for the list of available peripherals. DS70291D-page 10 11 PWM1L2/DAC1RN/RP13 PWM1H2/DAC1RP/RP12 25 9 PGEC2/PWM1L3/RP11 8 26 ...
Page 11
... REF OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 (1) SOSCI/RP4 /CN1/RB4 Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Controller Families” in this section for the list of available peripherals. © 2009 Microchip Technology Inc. PWM1L2/RP13 PWM1H2/RP12 25 PGEC2/PWM1L3/RP11 9 ...
Page 12
... Table of Contents dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 Product Families............................................. 6 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 21 3.0 CPU............................................................................................................................................................................................ 25 4.0 Memory Organization ................................................................................................................................................................. 39 5.0 Flash Program Memory .............................................................................................................................................................. 77 6.0 Resets ....................................................................................................................................................................................... 83 7.0 Interrupt Controller ..................................................................................................................................................................... 91 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 133 9 ...
Page 13
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. Preliminary DS70291D-page 13 ...
Page 14
... NOTES: DS70291D-page 14 Preliminary © 2009 Microchip Technology Inc. ...
Page 15
... Organization” in this data sheet for device-specific register and bit information. © 2009 Microchip Technology Inc. This document contains device specific information for the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 Digital Signal Controller (DSC) Devices. The dsPIC33F devices and contain extensive Digital Signal Processor (DSP) ...
Page 16
... FIGURE 1-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/ X04 BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks ...
Page 17
... ST ASDA1 I/O ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. PPS Description No Analog input channels. No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
Page 18
... DAC1 Positive Output. No DAC1 Output indicating middle point value (typically 1.65V). No DAC2 Negative Output. No DAC2 Positive Output. No DAC2 Output indicating middle point value (typically 1.65V). Analog = Analog input O = Output TTL = TTL input buffer Preliminary P = Power I = Input © 2009 Microchip Technology Inc. ...
Page 19
... Analog REF Analog REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2009 Microchip Technology Inc. PPS Description Yes PWM1 Fault A input. No PWM1 Low output 1 No PWM1 High output 1 No PWM1 Low output 2 ...
Page 20
... NOTES: DS70291D-page 20 Preliminary © 2009 Microchip Technology Inc. ...
Page 21
... Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 family of 16-bit Digital Signal Controllers (DSC) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • ...
Page 22
... Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin V IH for Preliminary and V ) and fast signal shown in Figure 2-2, it EXAMPLE OF MCLR PIN CONNECTIONS R R1 MCLR dsPIC33F JP C and V specifications are met and V specifications are met. IL © 2009 Microchip Technology Inc. is ...
Page 23
... REAL ICE™ In-Circuit Debugger User’s Guide” DS51616 ® • “Using MPLAB REAL ICE™” (poster) DS51749 © 2009 Microchip Technology Inc. 2.6 External Oscillator Pins Many DSCs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “ ...
Page 24
... Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect 10k resistor to V unused pins and drive the output to logic low. DS70291D-page Preliminary © 2009 Microchip Technology Inc. ...
Page 25
... As a result, three parameter instructions can be supported, allowing operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s dsPIC33FJ32MC302/304, and dsPIC33FJ128MCX02/X04 is shown in Figure 3-2. 3.2 Data Addressing Overview and The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred and Y data memory ...
Page 26
... A 40-bit barrel shifter is used to perform 16-bit left or right shift in a single cycle. The barrel shifter can be used by both MCU and DSP instructions. Preliminary dsPIC33FJ32MC302/304, and dsPIC33FJ32MC302/304, and © 2009 Microchip Technology Inc. ...
Page 27
... FIGURE 3-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 23 PCU PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Data Latch 24 Instruction Decode and Control Control Signals to Various Blocks © ...
Page 28
... FIGURE 3-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers AD39 DSP ACCA Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG OAB SAB DA SRH DS70291D-page 28 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back ...
Page 29
... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. © 2009 Microchip Technology Inc. R/C-0 R-0 (1) ...
Page 30
... Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). 4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB. DS70291D-page 30 (2) Preliminary © 2009 Microchip Technology Inc. ...
Page 31
... Program space visible in data space 0 = Program space not visible in data space Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R-0 ...
Page 32
... Integer mode enabled for DSP multiply ops 0 = Fractional mode enabled for DSP multiply ops Note 1: This bit is always read as ‘0’. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70291D-page 32 Preliminary © 2009 Microchip Technology Inc. ...
Page 33
... Automatic saturation on/off for ACCA (SATA) • Automatic saturation on/off for ACCB (SATB) • Automatic saturation on/off for writes to data memory (SATDW) • Accumulator Saturation mode selection (ACCSAT) A block diagram of the DSP engine is shown in Figure 3-3. Preliminary dsPIC33FJ32MC302/304, and can also perform inherent DS70291D-page 33 ...
Page 34
... – y • change • – x • – x • y 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary ACC Write Back Yes No No Yes No Yes Yes Round u Logic Zero Backfill © 2009 Microchip Technology Inc. ...
Page 35
... In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented. © 2009 Microchip Technology Inc. The adder/subtracter generates Overflow Status bits, SA/SB and OA/OB, which are latched and reflected in the STATUS register: • ...
Page 36
... Section 3.7.3.2 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2009 Microchip Technology Inc. to data saturation (see ...
Page 37
... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2009 Microchip Technology Inc. 3.7.4 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
Page 38
... NOTES: DS70291D-page 38 Preliminary © 2009 Microchip Technology Inc. ...
Page 39
... The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. and The memory map for the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 Figure 4-1. dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 GOTO Instruction ...
Page 40
... PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. dsPIC33FJ32MC302/304, and dsPIC33FJ128MCX02/X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...
Page 41
... The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). dsPIC33FJ32MC302/304, and dsPIC33FJ128MCX02/X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. ...
Page 42
... FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ32MC302/304 DEVICES WITH 4 KB RAM Address 2 Kbyte SFR Space 4 Kbyte SRAM Space Optionally Mapped into Program Memory 0xFFFF DS70291D-page 42 MSb 16 bits MSb LSb 0x0000 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0FFF 0x1001 Y Data RAM (Y) 0x13FF ...
Page 43
... Kbyte 0x17FF 0x1801 SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 0x8001 Optionally Mapped into Program Memory 0xFFFF © 2009 Microchip Technology Inc. LSb 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x17FE 0x1800 Y Data RAM (Y) 0x1FFE 0x2000 ...
Page 44
... Program Memory 0xFFFF DS70291D-page 44 LSb Address 16 bits MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x1FFE 0x27FE 0x2800 Y Data RAM (Y) 0x3FFE 0x4000 DMA RAM 0x47FE 0x4800 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2009 Microchip Technology Inc. ...
Page 45
... DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. Preliminary dsPIC33FJ32MC302/304, and DS70291D-page 45 ...
Page 46
TABLE 4-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
Page 47
TABLE 4-1: CPU CORE REGISTERS MAP (CONTINUED) SFR SFR Name Bit 15 Bit 14 Bit 13 Addr XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN DISICNT 0052 — — Legend unknown value on Reset, — ...
Page 48
... TABLE 4-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr 0060 CN15IE CN14IE CN13IE CN12IE CNEN1 0062 — CN30IE CN29IE — CNEN2 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU1 CNPU2 006A — ...
Page 49
TABLE 4-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR INTCON2 0082 ALTIVT DISI — — IFS0 0084 — DMA1IF AD1IF U1TXIF IFS1 0086 U2TXIF ...
Page 50
TABLE 4-5: TIMER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
Page 51
TABLE 4-7: OUTPUT COMPARE REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — OC3RS 018C ...
Page 52
TABLE 4-9: 2-OUTPUT PWM2 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 P2TCON 05C0 PTEN — PTSIDL P2TMR 05C2 PTDIR P2TPER 05C4 — P2SECMP 05C6 SEVTDIR PWM2CON1 05C8 — — — PWM2CON2 05CA — — ...
Page 53
TABLE 4-12: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
Page 54
... SPI2CON2 0264 FRMEN SPIFSD FRMPOL SPI2BUF 0268 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-17: ADC1 REGISTER MAP FOR dsPIC33FJ64MC202/802, dsPIC33FJ128MC202/802 AND dsPIC33FJ32MC302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 ...
Page 55
TABLE 4-18: ADC1 REGISTER MAP FOR dsPIC33FJ64MC204/804, dsPIC33FJ128MC204/804 AND dsPIC33FJ32MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 AD1CON1 0320 ADON — ADSIDL ADDMABM AD1CON2 0322 VCFG<2:0> — AD1CON3 0324 ADRC — — AD1CHS123 0326 ...
Page 56
TABLE 4-20: DMA REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA0CON 0380 CHEN SIZE DIR HALF DMA0REQ 0382 FORCE — — — DMA0STA 0384 DMA0STB 0386 DMA0PAD 0388 DMA0CNT 038A — — — — ...
Page 57
TABLE 4-20: DMA REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 DMA5PAD 03C4 DMA5CNT 03C6 — — — — DMA6CON 03C8 CHEN SIZE DIR HALF DMA6REQ 03CA FORCE — — — DMA6STA 03CC DMA6STB ...
Page 58
TABLE 4-21: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1CTRL1 0400 — — CSIDL ABAT C1CTRL2 0402 — — — C1VEC 0404 — ...
Page 59
TABLE 4-23: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 0400- 041E C1BUFPNT1 0420 F3BP<3:0> C1BUFPNT2 0422 F7BP<3:0> C1BUFPNT3 0424 F11BP<3:0> C1BUFPNT4 0426 F15BP<3:0> C1RXM0SID 0430 ...
Page 60
TABLE 4-23: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR dsPIC33FJ128MC802/804 AND dsPIC33FJ64MC802/804) (CONTINUED) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 C1RXF11EID 046E C1RXF12SID 0470 C1RXF12EID 0472 C1RXF13SID 0474 C1RXF13EID 0476 C1RXF14SID 0478 C1RXF14EID 047A C1RXF15SID ...
Page 61
TABLE 4-24: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR4 0688 — — — ...
Page 62
... TABLE 4-25: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — — — RPOR1 06C2 — — — RPOR2 06C4 — — — RPOR3 06C6 — — — RPOR4 06C8 — ...
Page 63
... TABLE 4-27: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 PMCON 0600 PMPEN — PSIDL ADRMUX<1:0> PMMODE 0602 BUSY IRQM<1:0> PMADDR ADDR15 CS1 0604 PMDOUT1 PMDOUT2 0606 PMDIN1 0608 PMPDIN2 060A PMAEN 060C — ...
Page 64
... C2EVT C1EVT CVRCON 0632 — — — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-32: PORTA REGISTER MAP FOR dsPIC33FJ128MC202/802, dsPIC33FJ64MC202/802 AND dsPIC33FJ32MC302 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — ...
Page 65
TABLE 4-33: PORTA REGISTER MAP FOR dsPIC33FJ128MC204/804, dsPIC33FJ64MC204/804 AND dsPIC33FJ32MC304 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISA 02C0 — — — — PORTA 02C2 — — — — LATA 02C4 — — — — ODCA ...
Page 66
TABLE 4-37: SECURITY REGISTER MAP FOR dsPIC33FJ128MC204/804 AND dsPIC33FJ64MC204/804 ONLY File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 BSRAM 0750 — — — — SSRAM 0752 — — — — Legend unknown value on Reset, ...
Page 67
... SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6 ...
Page 68
... ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Preliminary MAC INSTRUCTIONS Register Indirect with Register Offset Addressing mode is available only for W9 (in X space) and W11 (in Y space). OTHER INSTRUCTIONS © 2009 Microchip Technology Inc. ...
Page 69
... Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2009 Microchip Technology Inc. The length of a circular buffer is not directly specified determined by corresponding start and end addresses. The maximum possible length of the circular buffer is 32K words (64 Kbytes) ...
Page 70
... If Bit-Reversed Addressing has already been enabled by setting the BREN (XBREV<15>) bit, a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. N bytes, Preliminary should not be enabled © 2009 Microchip Technology Inc. ...
Page 71
... TABLE 4-41: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address © 2009 Microchip Technology Inc. Sequential Address Bit Locations Swapped Left-to-Right Around Center of Binary Value Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer Bit-Reversed Address Decimal Preliminary A0 Decimal ...
Page 72
... Aside from normal execution, dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • ...
Page 73
... Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. Program Counter 0 23 bits ...
Page 74
... TBLRDL.B (Wn<0> TBLRDL.B TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 0x800000 Only read operations are shown; write operations are also valid in the user memory area. Preliminary © 2009 Microchip Technology Inc. ...
Page 75
... PAG is mapped into the upper half of the data memory space... © 2009 Microchip Technology Inc. 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed ...
Page 76
... NOTES: DS70291D-page 76 Preliminary © 2009 Microchip Technology Inc. ...
Page 77
... Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire V range ...
Page 78
... RTSP Operation The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. Table 31-12 shows typical erase and programming times ...
Page 79
... Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2009 Microchip Technology Inc. (1) U-0 U-0 — — (1) ...
Page 80
... NVMKEY<7:0>: Key Register (write-only) bits DS70291D-page 80 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 81
... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2009 Microchip Technology Inc. 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
Page 82
... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2009 Microchip Technology Inc. ...
Page 83
... RESETS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- able from the Microchip (www ...
Page 84
... SWDTEN bit setting. DS70291D-page 84 (1) U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary U-0 R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 85
... Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2009 Microchip Technology Inc. (1) (CONTINUED) Preliminary ...
Page 86
... System Reset The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 family of devices have two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR Brown-out Reset (BOR cold Reset, the FNOSC configuration bits in the FOSC device configuration register selects the device clock source ...
Page 87
... GOTO instruction at the reset address, which redirects program execution to the appropriate start-up routine. 6: The Fail-Safe Clock Monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is ready and the delay T © 2009 Microchip Technology Inc. Vbor V BOR ...
Page 88
... DD ) for proper device operation. The BOR crosses DD has elapsed. The BOR ensures the voltage regulator output ) is programmed by PWRT Reset Timer Value Select bits in the POR Configuration + initiated each time V BOR PWRT trip point BOR © 2009 Microchip Technology Inc. DD ...
Page 89
... Reset state. This Reset state will not re- initialize the clock. The clock source in effect prior to the RESET instruction will remain. SYSRST is released at the next instruction cycle, and the reset vector fetch will commence. © 2009 Microchip Technology Inc BOR PWRT ...
Page 90
... RCON register value after a device Reset will be meaningful. Table 6-3 provides a summary of the reset flag bit operation. Set by: POR,BOR POR,BOR POR,BOR POR POR,BOR PWRSAV instruction, CLRWDT instruction, POR,BOR POR,BOR POR,BOR — — Preliminary Cleared by: © 2009 Microchip Technology Inc. ...
Page 91
... Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000 ...
Page 92
... FIGURE 7-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/ X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector DMA Error Trap Vector Reserved Reserved ...
Page 93
... Microchip Technology Inc. AIVT Address 0x000104 Reserved 0x000106 Oscillator Failure 0x000108 Address Error 0x00010A Stack Error 0x00010C Math Error 0x00010E DMA Error 0x000110 Reserved 0x000112 Reserved 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – ...
Page 94
... PWM2 – PWM2 Period Match 0x0001A8 FLTA2 – PWM2 Fault A 0x0001AA QEI2 – Position Counter Compare 0x0001AC Reserved 0x0001AE Reserved 0x0001B0 DAC1R – DAC1 Right Data Request 0x0001B2 DAC1L – DAC1 Left Data Request 0x0001B4-0x0001FE Reserved Preliminary Interrupt Source © 2009 Microchip Technology Inc. ...
Page 95
... Interrupt Control and Status Registers dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/X04 devices implement a total of 30 registers for the interrupt controller: • INTCON1 • INTCON2 • IFSx • IECx • IPCx • INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2 ...
Page 96
... R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2009 Microchip Technology Inc. ...
Page 97
... DMA controller error trap has occurred 0 = DMA controller error trap has not occurred bit 4 MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 COVAERR COVBERR OVATE ...
Page 98
... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70291D-page 98 Preliminary © 2009 Microchip Technology Inc. ...
Page 99
... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
Page 100
... DS70291D-page 100 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF R/W-0 R/W-0 R/W-0 DMA0IF T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 101
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. Preliminary DS70291D-page 101 ...
Page 102
... DS70291D-page 102 R/W-0 R/W-0 R/W-0 T5IF T4IF OC4IF R/W-0 R/W-0 R/W-0 INT1IF CNIF CMIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC3IF DMA2IF bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 103
... MI2C1IF: I2C1 Master Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2009 Microchip Technology Inc. Preliminary DS70291D-page 103 ...
Page 104
... U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 (1) (1) DMA3IF C1IF C1RXIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SPI2IF SPI2EIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 105
... Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 PWM1IF: PWM1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 R/W-0 — — QEI1IF U-0 ...
Page 106
... DS70291D-page 106 U-0 R/W-0 R/W-0 — QEI2IF FLTA2IF R/W-0 R/W-0 R/W-0 DMA6IF CRCIF U2EIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (2) (1) Preliminary R/W-0 U-0 PWM2IF — bit 8 R/W-0 U-0 U1EIF — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 107
... DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE R/W-0 ...
Page 108
... Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Flag Status bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70291D-page 108 Preliminary © 2009 Microchip Technology Inc. ...
Page 109
... INT1IE: External Interrupt 1 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T5IE T4IE OC4IE R/W-0 R/W-0 ...
Page 110
... Interrupt request not enabled bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70291D-page 110 Preliminary © 2009 Microchip Technology Inc. ...
Page 111
... Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPI2EIE: SPI2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Note 1: Interrupts are disabled on devices without ECAN™ modules. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — ...
Page 112
... DS70291D-page 112 U-0 U-0 R/W-0 — — QEI1IE U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2009 Microchip Technology Inc. R/W-0 U-0 PWM1IE — bit 8 U-0 U-0 — — bit Bit is unknown ...
Page 113
... U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: Interrupts are disabled on devices without ECAN™ modules. 2: Interrupts are disabled on devices without DAC modules. © 2009 Microchip Technology Inc. U-0 R/W-0 R/W-0 — QEI2IE FLTA2IE ...
Page 114
... Interrupt is priority 1 000 = Interrupt source is disabled DS70291D-page 114 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 115
... Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — ...
Page 116
... Interrupt is priority 1 000 = Interrupt source is disabled DS70291D-page 116 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 117
... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — ...
Page 118
... Interrupt is priority 1 000 = Interrupt source is disabled DS70291D-page 118 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 CMIP<2:0> bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
Page 120
... Interrupt is priority 1 000 = Interrupt source is disabled DS70291D-page 120 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC4IP<2:0> bit 8 R/W-0 R/W-0 DMA2IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 121
... Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ...
Page 122
... Note 1: Interrupts disabled on devices without ECAN™ modules. DS70291D-page 122 R/W-0 U-0 R/W-1 (1) — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) C1RXIP<2:0> bit 8 R/W-0 R/W-0 SPI2EIP<2:0> bit Bit is unknown (1) © 2009 Microchip Technology Inc. ...
Page 123
... Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 U-0 R/W-1 — ...
Page 124
... Unimplemented: Read as ‘0’ DS70291D-page 124 U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 DMA4IP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 125
... PWM1IP<2:0>: PWM1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. U-0 U-0 R/W-1 — — R/W-0 U-0 U-0 — ...
Page 126
... Unimplemented: Read as ‘0’ DS70291D-page 126 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RTCIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — ...
Page 128
... Note 1: Interrupts are disabled on devices without ECAN™ modules. DS70291D-page 128 U-0 U-0 R/W-1 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) C1TXIP<2:0> bit 8 R/W-0 R/W-0 DMA6IP<2:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. R/W-0 U-0 R/W-0 — R/W-0 U-0 U-0 — — ...
Page 130
... Note 1: Interrupts are disabled on devices without DAC modules. DS70291D-page 130 R/W-0 U-0 R/W-0 (1) — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) Preliminary R/W-0 R/W-0 (1) DAC1RIP<2:0> bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 131
... Unimplemented: Read as ‘0’ bit 6-0 VECNUM<6:0>: Vector Number of Pending Interrupt bits 0111111 = Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 © 2009 Microchip Technology Inc. U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM< ...
Page 132
... Only user interrupts with a priority level lower can be disabled. Trap sources (level 8-level 15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. Preliminary © 2009 Microchip Technology Inc. ...
Page 133
... CPU. To exploit the DMA capability, the corresponding user buffers or variables must be located in DMA RAM. The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 peripherals that can utilize DMA are listed in Table 8-1. DMAxPAD Register ...
Page 134
... Alternatively, an interrupt can be generated when half of the block has been filled. Peripheral Indirect Address DMA Controller DMA Channels DMA DS Bus Preliminary DMA Ready Peripheral 3 CPU DMA CPU DMA CPU DMA DMA DMA Ready Ready Peripheral 2 Peripheral 1 © 2009 Microchip Technology Inc. ...
Page 135
... DMACS1, are common to all DMAC channels. DMACS0 contains the DMA RAM and SFR write collision flags, XWCOLx and PWCOLx, respectively. DMACS1 indicates DMA channel and Ping-Pong mode status. © 2009 Microchip Technology Inc. The DMAxCON, DMAxREQ, DMAxCNT are all conventional read/write registers. ...
Page 136
... Continuous, Ping-Pong modes disabled DS70291D-page 136 R/W-0 R/W-0 HALF NULLW R/W-0 U-0 AMODE<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 R/W-0 — MODE<1:0> bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 137
... DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced DMA transfer is complete. 2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 138
... Bit is cleared R/W-0 R/W-0 R/W-0 STB<15:8> R/W-0 R/W-0 R/W-0 STB<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 139
... CNT<9:0>: DMA Transfer Count Register bits Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the DMA channel and should be avoided. 2: Number of DMA transfers = CNT<9:0> © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 PAD<15:8> ...
Page 140
... R/C-0 R/C-0 PWCOL4 PWCOL3 PWCOL2 R/C-0 R/C-0 R/C-0 XWCOL4 XWCOL3 XWCOL2 C = Clear only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/C-0 R/C-0 PWCOL1 PWCOL0 bit 8 R/C-0 R/C-0 XWCOL1 XWCOL0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 141
... No write collision detected bit 1 XWCOL1: Channel 1 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected bit 0 XWCOL0: Channel 0 DMA RAM Write Collision Flag bit 1 = Write collision detected write collision detected © 2009 Microchip Technology Inc. Preliminary DS70291D-page 141 ...
Page 142
... DMA0STA register selected DS70291D-page 142 U-0 R-1 R-1 — LSTCH<3:0> R-0 R-0 R-0 PPST4 PPST3 PPST2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R-1 R-1 bit 8 R-0 R-0 PPST1 PPST0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 143
... R-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-0 DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits © 2009 Microchip Technology Inc. R-0 R-0 R-0 DSADR<15:8> R-0 R-0 R-0 DSADR<7:0> Unimplemented bit, read as ‘0’ ...
Page 144
... NOTES: DS70291D-page 144 Preliminary © 2009 Microchip Technology Inc. ...
Page 145
... Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 oscillator system provides: FIGURE 9-1: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/ X04 OSCILLATOR SYSTEM DIAGRAM Primary Oscillator OSC1 POSCCLK ( OSC2 POSCMD< ...
Page 146
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected generate the device instruction clock (F the peripheral clock time base (F operating speed of the device, and speeds MHz are supported by the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 architecture. Instruction execution speed or device operating frequency, F ...
Page 147
... MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. FIGURE 9-2: dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/ X04 PLL BLOCK DIAGRAM Source (Crystal, External Clock or Internal RC) Note 1: This frequency range must be satisfied at all times. © 2009 Microchip Technology Inc. ...
Page 148
... DS70291D-page 148 Oscillator Source POSCMD<1:0> Internal xx Internal xx Internal xx ) Secondary xx Primary 10 Primary 01 Primary 00 Primary 10 Primary 01 Primary 00 Internal xx Internal xx Preliminary FNOSC<2:0> Note 1, 2 111 1 110 1 101 1 100 — 011 — 011 1 011 — 010 — 010 1 010 1 001 1 000 © 2009 Microchip Technology Inc. ...
Page 149
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. © 2009 Microchip Technology Inc. (1) R-0 ...
Page 150
... Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. DS70291D-page 150 (1) (CONTINUED) Preliminary © 2009 Microchip Technology Inc. ...
Page 151
... PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler) 00000 = Input/2 (default) 00001 = Input/3 • • • 11111 = Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. © 2009 Microchip Technology Inc. R/W-1 R/W-0 R/W-0 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE< ...
Page 152
... DS70291D-page 152 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) U-0 R/W-0 — PLLDIV<8> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 153
... Center frequency -12% (6.49 MHz) Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither characterized nor tested. © 2009 Microchip Technology Inc. U-0 U-0 U-0 — ...
Page 154
... U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) provides the source clock for the Auxiliary Clock Divider Preliminary R/W-0 R/W-0 R/W-0 APSTSCLR<2:0> bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 155
... Clock Switching Operation Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/ X04 devices have a safeguard lock built into the switch process. ...
Page 156
... NOTES: DS70291D-page 156 Preliminary © 2009 Microchip Technology Inc. ...
Page 157
... Instruction-Based Power-Saving family of Modes dsPIC33FJ32MC302/304, and dsPIC33FJ128MCX02/X04 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution. Idle mode halts the CPU and code ...
Page 158
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control regis- ters are already configured to enable mod- ule operation). Preliminary There are eight possible ® DSC © 2009 Microchip Technology Inc. ...
Page 159
... SPI2MD: SPI2 Module Disable bit 1 = SPI2 module is disabled 0 = SPI2 module is enabled bit 3 SPI1MD: SPI1 Module Disable bit 1 = SPI1 module is disabled 0 = SPI1 module is enabled bit 2 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 T2MD T1MD QEI1MD R/W-0 R/W-0 ...
Page 160
... REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED) bit 1 C1MD: ECAN1 Module Disable bit 1 = ECAN1 module is disabled 0 = ECAN1 module is enabled bit 0 AD1MD: ADC1 Module Disable bit 1 = ADC1 module is disabled 0 = ADC1 module is enabled DS70291D-page 160 Preliminary © 2009 Microchip Technology Inc. ...
Page 161
... OC2MD: Output Compare 2 Module Disable bit 1 = Output Compare 2 module is disabled 0 = Output Compare 2 module is enabled bit 0 OC1MD: Output Compare 1 Module Disable bit 1 = Output Compare 1 module is disabled 0 = Output Compare 1 module is enabled © 2009 Microchip Technology Inc. U-0 U-0 U-0 — — — U-0 ...
Page 162
... DS70291D-page 162 U-0 U-0 R/W-0 — — CMPMD R/W-0 U-0 U-0 PWM2MD — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 RTCCMD PMPMD bit 8 U-0 U-0 — — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 163
... I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 devices not intended compre- hensive reference source. To comple- ment the information in this data sheet, refer to “Section 10. (DS70193) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- able from ...
Page 164
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary dsPIC33FJ32MC302/304, © 2009 Microchip Technology Inc. ...
Page 165
... The association of a peripheral to a peripheral select- able pin is handled in two different ways, depending on whether an input or output is being mapped. © 2009 Microchip Technology Inc. 11.6.2.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral. A control register associated with a peripheral dictates the pin it is mapped to ...
Page 166
... RPINR23 CIRX RPINR26 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> T4CKR<4:0> T5CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> FLTA1R<4:0> FLTA2R<4:0> QEAIR<4:0> QEBIR<4:0> INDXIR<4:0> QEA2R<4:0> QEB2R<4:0> INDX2R<4:0> U1RXR<4:0> U1CTSR<4:0> U2RXR<4:0> U2CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> SDI2R<4:0> SCK2R<4:0> SS2R<4:0> CIRXR<4:0> © 2009 Microchip Technology Inc. ...
Page 167
... SDO2 SCK2 SS2 C1TX OC1 OC2 OC3 OC4 UPDN1 UPDN2 © 2009 Microchip Technology Inc. FIGURE 11-3: U1TX Output enable U1RTS Output enable 4 UPDN2 Output enable U1TX Output U1RTS Output 4 UPDN2 Output RPn tied to default port pin 00000 RPn tied to Comparator1 Output ...
Page 168
... Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows user applications unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. Preliminary © 2009 Microchip Technology Inc. ...
Page 169
... Peripheral Pin Select Registers The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/ X04 and dsPIC33FJ128MCX02/X04 family of devices implement 33 registers for remappable peripheral configuration: • 20 Input Remappable Peripheral Registers: - RPINR0-RPINR1, RPINR3-RPINR4, RPINR7, RPINR10-RPINR21, PRINR23, and PRINR26 • 13 Output Remappable Peripheral Registers: - RPOR0-RPOR12 Note: Input and Output Register values can only ...
Page 170
... Input tied to RP0 DS70291D-page 170 U-0 U-0 — — R/W-1 R/W-1 INTR2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 171
... T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ...
Page 172
... Input tied to RP1 00000 = Input tied to RP0 DS70291D-page 172 R/W-1 R/W-1 T5CKR<4:0> R/W-1 R/W-1 T4CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 173
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25. • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 IC1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 174
... Input tied to RP1 00000 = Input tied to RP0 DS70291D-page 174 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 175
... FLTA1R<4:0>: Assign PWM1 Fault (FLTA1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. U-0 U-0 — — R/W-1 R/W-1 OCFAR<4:0> Unimplemented bit, read as ‘0’ ...
Page 176
... Input tied to RP0 DS70291D-page 176 U-0 U-0 — — R/W-1 R/W-1 FLTA2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 177
... QEA1R<4:0>: Assign A(QEA1) to the corresponding pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 QEB1R<4:0> R/W-1 R/W-1 QEA1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 178
... Input tied to RP0 DS70291D-page 178 U-0 U-0 — — R/W-1 R/W-1 INDX1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 179
... QEA2R<4:0>: Assign A(QEA2) to the corresponding pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 QEB2R<4:0> R/W-1 R/W-1 QEA2R<4:0> Unimplemented bit, read as ‘0’ ...
Page 180
... Input tied to RP0 DS70291D-page 180 U-0 U-0 — — R/W-1 R/W-1 INDX2R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 181
... U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ...
Page 182
... Input tied to RP1 00000 = Input tied to RP0 DS70291D-page 182 R/W-1 R/W-1 U2CTSR<4:0> R/W-1 R/W-1 U2RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 R/W-1 bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 183
... SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 SDI1R<4:0> Unimplemented bit, read as ‘0’ ...
Page 184
... Input tied to RP0 DS70291D-page 184 U-0 U-0 — — R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 185
... SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin 11111 = Input tied to V 11001 = Input tied to RP25 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2009 Microchip Technology Inc. R/W-1 R/W-1 SCK2R<4:0> R/W-1 R/W-1 SDI2R<4:0> Unimplemented bit, read as ‘0’ ...
Page 186
... U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown (1) U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 R/W-1 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 187
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 11-2 for peripheral function numbers) © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 188
... Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 189
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 11-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 11-2 for peripheral function numbers) © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 190
... Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 191
... Unimplemented: Read as ‘0’ bit 4-0 RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP17R<4:0> R/W-0 ...
Page 192
... Bit is cleared R/W-0 R/W-0 R/W-0 RP23R<4:0> R/W-0 R/W-0 R/W-0 RP22R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown (1) R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 193
... Unimplemented: Read as ‘0’ bit 4-0 RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 11-2 for peripheral function numbers) Note 1: This register is implemented in 44-pin devices only. © 2009 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 RP25R<4:0> R/W-0 ...
Page 194
... NOTES: DS70291D-page 194 Preliminary © 2009 Microchip Technology Inc. ...
Page 195
... TIMER1 Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to “Section 11. Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is avail- able from the Microchip (www ...
Page 196
... DS70291D-page 196 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 197
... TIMER2/3 AND TIMER4/5 FEATURE Note 1: This data sheet summarizes the features of the dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 dsPIC33FJ128MCX02/X04 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to “Section 11. Timers” (DS70205) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www ...
Page 198
... The timer value at any point is stored in the register pair, TMR3:TMR2 or TMR5:TMR4, which always contains the most significant word of the count, while TMR2 or TMR4 contains the least significant word. Preliminary 32-BIT TIMER TYPE C Timer (msw) Timer3 Timer5 © 2009 Microchip Technology Inc. ...
Page 199
... F CY (/n) TCKPS<1:0> Prescaler Sync (/n) TxCK TCKPS<1:0> Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers. 2: Timer Type B Timer ( and 4). 3: Timer Type C Timer ( and 5). © 2009 Microchip Technology Inc. Falling Edge Detect PRy PRx Comparator 10 lsw TMRx TMRy 00 x1 TMRyHLD ...
Page 200
... DS70291D-page 200 U-0 U-0 — — R/W-0 R/W-0 TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /2) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2009 Microchip Technology Inc. ...