PIC16C63A-04I/SS Microchip Technology, PIC16C63A-04I/SS Datasheet - Page 65

• Manufacturer Part Number: PIC16C63A-04I/SS
• Description: IC MCU OTP 4KX14 PWM 28SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C63A-04I/SS

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• For Use With: AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

11.0
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
REGISTER 11-1:
2000 Microchip Technology Inc.
ADDRESSABLE UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of Transmit Data. Can be parity bit.
bit 7
Legend:
R = Readable bit
-n = Value at POR
R/W-0
CSRC
Note:
SREN/CREN overrides TXEN in SYNC mode.
R/W-0
TX9
R/W-0
TXEN
W = Writable bit
’1’ = Bit is set
PIC16C63A/65B/73B/74B
R/W-0
SYNC
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
The USART can be configured in the following modes:
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be
set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the universal synchronous asynchro-
nous receiver transmitter.
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
U-0
—
R/W-0
BRGH
x = Bit is unknown
TRMT
R-1
DS30605C-page 65
R/W-0
TX9D
bit 0