PIC18F4420-I/PT Microchip Technology, PIC18F4420-I/PT Datasheet - Page 40
![IC MCU FLASH 8KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4420-I/PT
Manufacturer Part Number
PIC18F4420-I/PT
Description
IC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2420-IML.pdf
(412 pages)
3.PIC18F2420-IML.pdf
(16 pages)
4.PIC18F2420-IML.pdf
(8 pages)
5.PIC18F2420-IML.pdf
(6 pages)
6.PIC18F2420-IML.pdf
(8 pages)
7.PIC18F2420-IML.pdf
(4 pages)
8.PIC18F4420-IP.pdf
(390 pages)
Specifications of PIC18F4420-I/PT
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
MSSP/SPI/I2C/PSP/USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4420-I/PT
Manufacturer:
MICROCHIPS
Quantity:
661
Company:
Part Number:
PIC18F4420-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4420-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC18F2221-ISO PDF datasheet
- PIC18F2420-IML PDF datasheet #2
- PIC18F2420-IML PDF datasheet #3
- PIC18F2420-IML PDF datasheet #4
- PIC18F2420-IML PDF datasheet #5
- PIC18F2420-IML PDF datasheet #6
- PIC18F2420-IML PDF datasheet #7
- PIC18F4420-IP PDF datasheet #8
- Current page: 40 of 390
- Download datasheet (8Mb)
PIC18F2420/2520/4420/4520
3.4.1
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 configuration bits. The OSTS bit
remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-8).
3.4.2
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
FIGURE 3-7:
FIGURE 3-8:
DS39631A-page 38
CPU Clock
Peripheral
Program
Counter
CPU Clock
Peripheral
OSC1
Clock
Program
Counter
OSC1
Clock
PRI_IDLE MODE
SEC_IDLE MODE
Q1
Q1
TRANSITION TIMING FOR ENTRY TO IDLE MODE
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q2
Wake Event
PC
Q3
T
CSD
Q4
CSD
Q1
is
PC + 2
PC
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS1:SCS0 bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval
of T
cuting code being clocked by the Timer1 oscillator. The
IDLEN and SCS bits are not affected by the wake-up;
the Timer1 oscillator continues to run (see Figure 3-8).
Note:
CSD
following the wake event, the CPU begins exe-
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet
running, peripheral clocks will be delayed
until the oscillator has started. In such sit-
uations, initial oscillator operation is far
from stable and unpredictable operation
may result.
Q2
2004 Microchip Technology Inc.
Q3
Q4
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