PIC18F2420-I/ML Microchip Technology, PIC18F2420-I/ML Datasheet - Page 151

IC PIC MCU FLASH 8KX16 28QFN

PIC18F2420-I/ML

Manufacturer Part Number
PIC18F2420-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F2420-I/ML

Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT28QFN4 - SOCKET TRANS ICE 28QFN W/CABLEAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2420-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
16.4
The Enhanced PWM mode provides additional PWM
output options for a broader range of control applica-
tions. The module is a backward compatible version of
the standard CCP module and offers up to four outputs,
designated P1A through P1D. Users are also able to
select the polarity of the signal (either active-high or
active-low). The module’s output mode and polarity are
configured
CCP1M3:CCP1M0 bits of the CCP1CON register.
Figure 16-1 shows a simplified block diagram of PWM
operation. All control registers are double-buffered and
are loaded at the beginning of a new PWM cycle (the
period boundary when Timer2 resets) in order to pre-
vent glitches on any of the outputs. The exception is the
PWM Delay register, PWM1CON, which is loaded at
either the duty cycle boundary or the period boundary
(whichever comes first). Because of the buffering, the
module waits until the assigned timer resets, instead of
starting immediately. This means that enhanced PWM
waveforms do not exactly match the standard PWM
waveforms, but are instead offset by one full instruction
cycle (4 T
As before, the user must manually configure the
appropriate TRIS bits for output.
FIGURE 16-1:
 2004 Microchip Technology Inc.
Enhanced PWM Mode
OSC
Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit
CCPR1H (Slave)
Duty Cycle Registers
).
Comparator
by
CCPR1L
time base.
PR2
TMR2
Comparator
setting
SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE
(Note 1)
the
Clear Timer,
set CCP1 pin and
latch D.C.
CCP1CON<5:4>
P1M1:P1M0
R
S
PIC18F2420/2520/4420/4520
P1M1<1:0>
Q
and
Preliminary
PWM1CON
Controller
16.4.1
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following equation.
EQUATION 16-1:
PWM frequency is defined as 1/[PWM period]. When
TMR2 is equal to PR2, the following three events occur
on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (if PWM duty cycle = 0%, the
• The PWM duty cycle is copied from CCPR1L into
Output
2
CCP1/P1A
CCP1 pin will not be set)
CCPR1H
Note:
P1B
P1C
P1D
PWM Period =
CCP1M<3:0>
4
PWM PERIOD
The Timer2 postscaler (see Section 13.0
“Timer2 Module”) is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
TRISx<x>
TRISx<x>
TRISx<x>
TRISx<x>
[(PR2) + 1] • 4 • T
(TMR2 Prescale Value)
DS39631A-page 149
CCP1/P1A
P1B
P1C
P1D
OSC

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