PIC16C63A-20/SS Microchip Technology, PIC16C63A-20/SS Datasheet - Page 63

IC MCU OTP 4KX14 PWM 28SSOP

PIC16C63A-20/SS

Manufacturer Part Number
PIC16C63A-20/SS
Description
IC MCU OTP 4KX14 PWM 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Cr

Specifications of PIC16C63A-20/SS

Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16C63A-20/SS
Manufacturer:
IR
Quantity:
500
Part Number:
PIC16C63A-20/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
10.3.1.3
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 10-7).
FIGURE 10-7:
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
2000 Microchip Technology Inc.
S
Transmission
A7
Data in
sampled
1
A6
2
I
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
3
A4
4
A3
5
A2
6
A1
7
R/W = 1
8
9
PIC16C63A/65B/73B/74B
ACK
responds to SSPIF
SCL held low
while CPU
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK), then the data transfer is complete. When the
ACK is latched by the slave, the slave logic is reset
(resets SSPSTAT register) and the slave then monitors
for another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR reg-
ister. Then pin RC3/SCK/SCL should be enabled by
setting bit CKP.
D7
SSPBUF is written in software
1
D6
2
Cleared in software
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
D5
3
D4
4
Transmitting Data
D3
5
D2
6
From SSP Interrupt
Service Routine
D1
7
D0
8
DS30605C-page 63
ACK
9
P

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