PIC18F87J90-I/PT Microchip Technology, PIC18F87J90-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F87J90-I/PT
• Description: IC PIC MCU FLASH 128KB 80-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J90-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 67
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3923 B
• Interface Type: AUSART, EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 67
• Number Of Timers: 4
• Operating Supply Voltage: 2.65 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164323 - MODULE SKT FOR 100TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Silicon Errata Issues
1. Module: MSSP (I
 2010 Microchip Technology Inc.
Note:
In extremely rare cases when configured for I
slave reception, the MSSP module may not
receive the correct data. This occurs only if the
Serial Receive/Transmit Buffer register (SSPBUF)
is not read within a window after the SSPIF
interrupt (PIR1<3>) has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPIF bit is set, read the
Affected Silicon Revisions
A1
clock stretching feature.
This
(SSPCON2<0>).
SSPBUF before the first rising clock edge of the
next byte being received.
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A3).
A3
X
is
done
2
C slave reception, enable the
2
by
C™ Slave)
setting
the
SEN
2
C™
bit
PIC18F87J90 FAMILY
2. Module: Enhanced Universal
3. Module: Real-Time Clock and Calendar
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (SPEN bit
• The EUSART is re-enabled (RCSTAx<7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2 T
1. Disable
2. Disable the EUSART (RCSTAx<7> = 0).
3. Re-enable the EUSART (RCSTAx<7> = 1).
4. Re-enable receive interrupts (PIE1<5> = 1).
5. Execute a NOP instruction.
Affected Silicon Revisions
The INTRC is not automatically enabled as the
clock source for the RTCC module when the
INTRC clock is selected (CONFIG3L<1> = 0) and
the RTCC module is enabled (RTCCFG<7> = 1).
Work around
In order to enable the INTRC, at least one of the
following has to be enabled:
1. Watchdog Timer Enable bit
2. Two-Speed Start-up Enable bit (IESO,
3. Fail-Safe Clock Monitor Enable bit (FCMEN,
Affected Silicon Revisions
A1
A1
(RCSTAx<7>) = 0)
X
X
(PIE1<5>) = 0).
CONFIG1L<0>).
CONFIG2L<7>).
CONFIG2L<6>).
(This is the first T
(This is the second T
A3
A3
X
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
(RTCC)
delay after re-enabling the EUSART.
receive
CY
interrupts
delay).
CY
delay).
DS80432E-page 3
(RCxIE
(WDTEN,
bit