PIC16F737-I/SP Microchip Technology, PIC16F737-I/SP Datasheet - Page 133

• Manufacturer Part Number: PIC16F737-I/SP
• Description: IC PIC MCU FLASH 4KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F737-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: AUSART/CCP/I2C/MSSP/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3DBF777 - BOARD DAUGHTER ICEPIC3
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 10-31:
FIGURE 10-32:
 2004 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
BCLIF
SSPIF
SDA
PEN
SDA
SCL
PEN
BCLIF
P
SSPIF
SCL
P
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 10-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 10-32).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
PIC16F7X7
SDA sampled
low after T
set BCLIF
DS30498C-page 131
‘0’
‘0’
‘0’
‘0’
BRG
,