PIC18F27J53-I/SP Microchip Technology, PIC18F27J53-I/SP Datasheet - Page 124

• Manufacturer Part Number: PIC18F27J53-I/SP
• Description: IC PIC MCU 128KB FLASH 28SPDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F27J53-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: *
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.8 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 8
• Operating Supply Voltage: 2.15 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Controller Family/series: PIC18
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, SPI, USART
• Digital Ic Case Style: DIP
• Supply Voltage Range: 1.8V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18(L)F2X/4XK22
REGISTER 9-10:
DS41412D-page 124
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OSCFIE
R/W-0
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
C1IE: Comparator C1 Interrupt Enable bit
1 = Enabled
0 = Disabled
C2IE: Comparator C2 Interrupt Enable bit
1 = Enabled
0 = Disabled
EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL1IE: MSSP1 Bus Collision Interrupt Enable bit
1 = Enabled
0 = Disabled
HLVDIE: Low-Voltage Detect Interrupt Enable bit
1 = Enabled
0 = Disabled
TMR3IE: TMR3 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
R/W-0
C1IE
PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2
W = Writable bit
‘1’ = Bit is set
R/W-0
C2IE
R/W-0
EEIE
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BCL1IE
R/W-0
HLVDIE
R/W-0
 2010 Microchip Technology Inc.
x = Bit is unknown
TMR3IE
R/W-0
CCP2IE
R/W-0
bit 0