PIC16F84A-04/P Microchip Technology, PIC16F84A-04/P Datasheet - Page 529

• Manufacturer Part Number: PIC16F84A-04/P
• Description: IC MCU FLASH 1KX14 EE 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F84A-04/P

• Program Memory Type: FLASH
• Program Memory Size: 1.75KB (1K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Eeprom Size: 64 x 8
• Ram Size: 68 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 68 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F84A - BOARD DAUGHTER ICEPIC3DVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

29.4
1997 Microchip Technology Inc.
Q Cycle Activity
Tosc
Each instruction cycle (Tcy) is comprised of four Q cycles (Q1-Q4). The Q cycle is the same as
the device oscillator cycle (T
Read, Process Data, Write etc., of each instruction cycle. The following diagram shows the rela-
tionship of the Q cycles to the instruction cycle.
The four Q cycles that make up an instruction cycle (Tcy) can be generalized as:
Each instruction will show the detailed Q cycle operation for the instruction.
Figure 29-2: Q Cycle Activity
Q1: Instruction Decode Cycle or forced No Operation
Q2: Instruction Read Cycle or No Operation
Q3: Process the Data
Q4: Instruction Write Cycle or No Operation
Q1
Q2
Tcy1
Q3
Q4
Section 29. Instruction Set
OSC
Q1
). The Q cycles provide the timing/designation for the Decode,
Q2
Tcy2
Q3
Q4
Q1
Q2
Tcy3
Q3
Q4
DS31029A-page 29-7
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