PIC24FJ64GA102-I/ML Microchip Technology, PIC24FJ64GA102-I/ML Datasheet - Page 115
![IC MCU 16BIT 64KB FLASH 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ64GA102-I/ML
Manufacturer Part Number
PIC24FJ64GA102-I/ML
Description
IC MCU 16BIT 64KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(308 pages)
2.PIC24FJ32GA102-ISP.pdf
(12 pages)
3.PIC24FJ32GA102-ISP.pdf
(48 pages)
4.PIC24FJ64GA104-IML.pdf
(300 pages)
Specifications of PIC24FJ64GA102-I/ML
Core Size
16-Bit
Program Memory Size
64KB (22K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC24
Ram Memory Size
8KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, LIN, SPI, USART
No. Of Pwm Channels
5
Embedded Interface Type
I2C, LIN, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ64GA102-I/ML
Manufacturer:
MAXIM
Quantity:
15 620
- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GA102-ISP PDF datasheet #3
- PIC24FJ64GA104-IML PDF datasheet #4
- Current page: 115 of 300
- Download datasheet (5Mb)
REGISTER 9-1:
© 2009 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0, HC
DSEN
U-0
—
2:
3:
(1)
These bits are reset only in the case of a POR event outside of Deep Sleep mode.
Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.
This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.
DSEN: Deep Sleep Enable bit
1 = Device enters Deep Sleep when PWRSAV #0 is executed in the next instruction
0 = Device enters normal Sleep when PWRSAV #0 is executed
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event Status bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was disabled or was active and did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Deep Sleep Release bit
1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT
0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the
and TRIS configuration
LAT and TRIS configurations, and the SOSCEN bit.
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U-0
U-0
—
—
(1)
PIC24FJ64GA104 FAMILY
Preliminary
U-0
U-0
—
—
(1,2,3)
C = Clearable bit
‘0’ = Bit is cleared
HCS = Hardware Clearable/Settable bit
U-0
U-0
—
—
(1,2)
U-0
U-0
—
—
U = Unimplemented, read as ‘0’
x = Bit is unknown
R/W-0, HCS
DSBOR
U-0
—
(1,2,3)
DS39951B-page 113
RELEASE
R/C-0, HS
U-0
—
(1,2)
bit 8
bit 0
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