PIC18F6310-I/PT Microchip Technology, PIC18F6310-I/PT Datasheet - Page 89
![IC PIC MCU FLASH 4KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6310-I/PT
Manufacturer Part Number
PIC18F6310-I/PT
Description
IC PIC MCU FLASH 4KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F6310-IPT.pdf
(412 pages)
2.PIC18F6310-IPT.pdf
(16 pages)
3.PIC18F6310-IPT.pdf
(4 pages)
4.PIC18F6310-IPT.pdf
(28 pages)
5.PIC18F6310-IPT.pdf
(6 pages)
6.PIC18F6310-IPT.pdf
(4 pages)
7.PIC18F8310-IPT.pdf
(404 pages)
Specifications of PIC18F6310-I/PT
Program Memory Type
FLASH
Program Memory Size
8KB (4K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI/I2C/EUSART/AUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
4
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6310-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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7.0
For PIC18FX310/X410 devices, the on-chip program
memory is implemented as read-only memory. It is
readable over the entire V
operation; it cannot be written to or erased. Reads from
program memory are executed one byte at a time.
PIC18F8410 devices also implement the ability to read,
write to and execute code from external memory
devices using the external memory interface. In this
implementation, external memory is used as all or part
of the program memory space. The operation of the
physical interface is discussed in
Memory
In all devices, a value written to the program memory
space does not need to be a valid instruction.
Executing a program memory location that forms an
invalid instruction results in a NOP.
7.1
To read and write to the program memory space, there
are two operations that allow the processor to move
bytes between the program memory space and the
data RAM: table read (TBLRD) and table write (TBLWT).
FIGURE 7-1:
2010 Microchip Technology Inc.
PROGRAM MEMORY
Table Reads and Table Writes
Interface”.
Note 1: The Table Pointer register points to a byte in the program memory space.
Instruction: TBLRD*
Instruction: TBLWT*
TBLPTRU
TBLPTRU
2: Data is actually written to the memory location by the memory write algorithm. See
“Writing to Program Memory Space (PIC18F8310/8410 only)”
Table Pointer
Table Pointer
TABLE READ AND TABLE WRITE OPERATIONS
TBLPTRH TBLPTRL
TBLPTRH TBLPTRL
DD
Section 8.0 “External
range during normal
(1)
(1)
PIC18F6310/6410/8310/8410
Program Memory Space
Program Memory Space
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table read operations retrieve data from program
memory and places it into the data RAM space. Table
write operations place data from the data memory
space on the external data bus. The actual process of
writing the data to the particular memory device is
determined by the requirements of the device itself.
Figure 7-1
program memory and data RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word-aligned. Therefore, a table block
can start and end at any byte address. If a table write is
being used to write executable code into an external
program memory, program instructions will need to be
word-aligned.
Note:
shows the table operations as they relate to
Although it cannot be used in PIC18F6310
devices in normal operation, the TBLWT
instruction is still implemented in the
instruction set. Executing the instruction
takes two instruction cycles, but effectively
results in a NOP.
The TBLWT instruction is available in
programming modes and is used during
In-Circuit Serial Programming (ICSP).
for more information.
Data Memory Space
Table Latch (8-bit)
Data Memory Space
Table Latch (8-bit)
TABLAT
TABLAT
Section 7.4
DS39635C-page 89
(2)
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