PIC18LF27J13-I/SP Microchip Technology, PIC18LF27J13-I/SP Datasheet - Page 2

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PIC18LF27J13-I/SP

Manufacturer Part Number
PIC18LF27J13-I/SP
Description
IC PIC MCU 128KB FLASH 28SPDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18LF27J13-I/SP

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Type
FLASH
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.75 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Controller Family/series
PIC18
Cpu Speed
48MHz
Digital Ic Case Style
DIP
Supply Voltage Range
1.8V To 3.6V
Embedded Interface Type
I2C, SPI, USART
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F47J13 FAMILY
TABLE 2:
DS80503D-page 2
CTMU
Oscillator
Configurations
ADC
MSSP
MSSP
EUSART
Note 1:
Module
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY
Constant
Current
Source
PLL
A/D
I
Mode
I
Reception
Enable/
Disable
2
2
C™
C Slave
Feature
Number
Item
1.
2.
3.
4.
5.
6.
Band gap must be manually enabled before
using the CTMU.
PLL can not be enabled unless the 8 or
4 MHz INTOSC option is set.
ANx pin may output a pull-up pulse during
acquisition.
If a Stop condition occurs in the middle of an
address or data reception, there will be
issues with the SCL clock stream and RCEN
bit.
In I
problems receiving correct data.
If interrupts are enabled, disabling and
re-enabling the module requires a 2 T
delay.
2
C slave reception, the module may have
Issue Summary
CY
 2011 Microchip Technology Inc.
A1
Affected Revisions
X
X
X
X
X
X
(1)

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